Ke Huang
Affiliations:- Tsinghua University, Institute of Microelectronics, Beijing, China
- University of Electronic Science and Technology of China, Institute of Microelctronics, Sichuan, China (former)
According to our database1,
Ke Huang
authored at least 11 papers
between 2012 and 2015.
Collaborative distances:
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Bibliography
2015
A 80 mW 40 Gb/s Transmitter With Automatic Serializing Time Window Search and 2-tap Pre-Emphasis in 65 nm CMOS Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
A 75mW 50Gbps SerDes transmitter with automatic serializing time window search in 65nm CMOS technology.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
A 6.4 Gb/s source synchronous receiver core with variable offset equalizer in 65nm CMOS.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013
A 10-Gb/s simplified transceiver with a quarter-rate 4-tap decision feedback equalizer in 0.18-μm CMOS technology.
Proceedings of the IEEE 10th International Conference on ASIC, 2013
Proceedings of the IEEE 10th International Conference on ASIC, 2013
2012
A novel clock and data recovery scheme for 10Gbps source synchronous receiver in 65nm CMOS.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
A 10Gbps CDR based on phase interpolator for source synchronous receiver in 65nm CMOS.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012