Liji Wu

According to our database1, Liji Wu authored at least 54 papers between 2011 and 2018.

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Bibliography

2018
A Novel Multiple-Bits Collision Attack Based on Double Detection with Error-Tolerant Mechanism.
Security and Communication Networks, 2018

2017
A 50Gb/s repeater and 2 × 50Gb/s 27-1 PRBS generator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Side Channel Attack on SM4 Algorithm with Ensemble Method.
Proceedings of the 13th International Conference on Computational Intelligence and Security, 2017

An efficient HMAC processor based on the SHA-3 HASH function.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
A 70 mW 25 Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset With 40 dB of Equalization in 65 nm CMOS Technology.
IEEE Trans. on Circuits and Systems, 2016

A new zero value attack combined fault sensitivity analysis on masked AES.
Microprocessors and Microsystems - Embedded Hardware Design, 2016

A High Precision Multi-Cell Battery Voltage Detecting Circuit for Battery Management Systems.
Proceedings of the IEEE 83rd Vehicular Technology Conference, 2016

A Novel Method of Correlation Power Analysis on SM4 Hardware Implementation.
Proceedings of the 12th International Conference on Computational Intelligence and Security, 2016

Research on Side Channel Attack for USB Key.
Proceedings of the 12th International Conference on Computational Intelligence and Security, 2016

2015
A novel bit scalable leakage model based on genetic algorithm.
Security and Communication Networks, 2015

Double Sieve Collision Attack Based on Bitwise Detection.
TIIS, 2015

A high-performance elliptic curve cryptographic coprocessor with side channel analysis countermeasures for smart IC card.
IEICE Electronic Express, 2015

Efficient collision attacks on smart card implementations of masked AES.
SCIENCE CHINA Information Sciences, 2015

Template attack on masking AES based on fault sensitivity analysis.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015

A 48mW 15-to-28Gb/s source-synchronous receiver with adaptive DFE using hybrid alternate clock scheme and baud-rate CDR in 65nm CMOS.
Proceedings of the ESSCIRC Conference 2015, 2015

A Template Attack-Resistant Masking Scheme for RC4 Based on FPGA.
Proceedings of the 11th International Conference on Computational Intelligence and Security, 2015

A Novel Detection Algorithm for Ring Oscillator Network Based Hardware Trojan Detection with Tactful FPGA Implementation.
Proceedings of the 11th International Conference on Computational Intelligence and Security, 2015

Software Hardware Co-design for Side-Channel Analysis Platform on Security Chips.
Proceedings of the 11th International Conference on Computational Intelligence and Security, 2015

A 4×20-Gb/s 0.86pJ/b/lane 2-tap-FFE source-series-terminated transmitter with far-end crosstalk cancellation and divider-less clock generation in 65nm CMOS.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

Transient-Steady Effect Attack on Block Ciphers.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2015, 2015

A 125KHz low frequency power recovery circuit for battery-less TPMS SoC.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A novel oscillator-based TRNG for smart IC card.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
A 4.8-mW/Gb/s 9.6-Gb/s 5 + 1-Lane Source-Synchronous Transmitter in 65-nm Bulk CMOS.
IEEE Trans. on Circuits and Systems, 2014

Improved Leakage Model Based on Genetic Algorithm.
IACR Cryptology ePrint Archive, 2014

Scalable behavior modeling for SCR based ESD protection structures for circuit simulation.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A Novel Template Attack on wNAF Algorithm of ECC.
Proceedings of the Tenth International Conference on Computational Intelligence and Security, 2014

A Novel Subspace Template Attack Based on Symmetric Cross Entropy Criterion.
Proceedings of the Tenth International Conference on Computational Intelligence and Security, 2014

Wavelet-Based Noise Reduction in Power Analysis Attack.
Proceedings of the Tenth International Conference on Computational Intelligence and Security, 2014

Design of a Masked S-Box for SM4 Based on Composite Field.
Proceedings of the Tenth International Conference on Computational Intelligence and Security, 2014

Adaptive Chosen-Plaintext Correlation Power Analysis.
Proceedings of the Tenth International Conference on Computational Intelligence and Security, 2014

Hardware Design and Implementation of SM3 Hash Algorithm for Financial IC Card.
Proceedings of the Tenth International Conference on Computational Intelligence and Security, 2014

Algorithm-Based Countermeasures against Power Analysis Attacks for Public-Key Cryptography SM2.
Proceedings of the Tenth International Conference on Computational Intelligence and Security, 2014

2013
A 10 Gbps in-line network security processor based on configurable hetero-multi-cores.
Journal of Zhejiang University - Science C, 2013

An IPSec Accelerator Design for a 10Gbps In-Line Security Network Processor.
JCP, 2013

Power analysis attacks on wireless sensor nodes using CPU smart card.
Proceedings of the 22nd Wireless and Optical Communication Conference, 2013

A 10Gbps in-line Network Security Processor with a 32-bit embedded CPU.
Proceedings of the 22nd Wireless and Optical Communication Conference, 2013

Efficient Countermeasures against Fault Attacks for 3DES Crypto Engine in Bank IC Card.
Proceedings of the Ninth International Conference on Computational Intelligence and Security, 2013

A 10-Gb/s simplified transceiver with a quarter-rate 4-tap decision feedback equalizer in 0.18-μm CMOS technology.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

A novel ESD device for Whole-Chip ESD protection network of TPMS mixed signal SoC.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

Design and implementation of RSA for dual interface bank IC card.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

Design of 13.56MHz power recovery circuit with signal transmission for contactless bank IC card.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

Mixed-signal SoC design and low power research for tire pressure monitoring systems.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
A High-Speed SHA-1 IP Core for 10 Gbps Ethernet Security Processor.
Proceedings of the Eighth International Conference on Computational Intelligence and Security, 2012

Design of Monitor and Protect Circuits against FIB Attack on Chip Security.
Proceedings of the Eighth International Conference on Computational Intelligence and Security, 2012

Design and Implementation of a Fault Attack Platform for Smart IC Card.
Proceedings of the Eighth International Conference on Computational Intelligence and Security, 2012

2011
A Low Power LDO Design for Battery-Less TPMS.
Proceedings of the Frontiers in Computer Education [International Conference on Frontiers in Computer Education, 2011

A Configurable IPSec Processor for High Performance In-Line Security Network Processor.
Proceedings of the Seventh International Conference on Computational Intelligence and Security, 2011

Design and Implementation of an Electromagnetic Analysis System for Smart Cards.
Proceedings of the Seventh International Conference on Computational Intelligence and Security, 2011

A passive UHF tag for RFID-based train axle temperature measurement system.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

A low-power 433MHz transmitter for battery-less Tire Pressure Monitoring System.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Research on testing of 32-bit CPU based SiP.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Reflection analysis of signal transmission in 32-bit CPU based SiP.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

New power rail ESD clamp design with current starving technology.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Design and implementation of a low Power Java Coprocessor for dual-interface IC Bank Card.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011


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