Keiichi Koike

According to our database, Keiichi Koike authored at least 4 papers between 1993 and 2010.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2010

A 2Gb/s network processor with a 24mW IPsec offload for residential gateways.

Yukikuni Nishida, Kenji Kawai, Keiichi Koike

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

1999

A 557-mW, 2.5-Gbit/s SONET/SDH regenerator-section terminating LSI chip using low-power bipolar-LSI design.

Kenji Kawai, Keiichi Koike, Yuichiro Takei, Akira Onozawa, Hitoshi Obara, Haruhiko Ichino

IEEE J. Solid State Circuits, 1999

1998

High-speed, low-power, bipolar standard cell design methodology for Gbit/s signal processing.

Keiichi Koike, Kenji Kawai, Akira Onozawa, Yuichiro Takei, Yoshiji Kobayashi, Haruhiko Ichino

IEEE J. Solid State Circuits, 1998

1993

An Algorithm to Eliminate All Complex Triangles in a Maximal Planar Graph for Use in VLSI floorplan.

Shuji Tsukiyama, Keiichi Koike, Isao Shirakawa

Proceedings of the Algorithmic Aspects of VLSI Layout, 1993