Shuji Tsukiyama

According to our database1, Shuji Tsukiyama authored at least 41 papers between 1977 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2019
Gaussian Mixture Reduction Methods Using Support Vector Machine.
Proceedings of the TENCON 2019, 2019

2017
A New Algorithm to Determine Covariance in Statistical Maximum for Gaussian Mixture Model.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Approximating the maximum of Gaussians by a Gaussian mixture model for statistical designs.
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017

2016
A New Algorithm for Reducing Components of a Gaussian Mixture Model.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

2015
A statistical method for analyzing lifetime of a series-connected battery cells.
Proceedings of the 15th International Symposium on Communications and Information Technologies, 2015

2013
A New Delay Distribution Model with a Half Triangular Distribution for Statistical Static Timing Analysis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

An implementation and evaluation of Backward Euler algorithm to GPGPU power grid circuit simulation.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

2011
A Statistical Maximum Algorithm for Gaussian Mixture Models Considering the Cumulative Distribution Function Curve.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

A power grid optimization algorithm considering timing degradation by NBTI.
Proceedings of the International SoC Design Conference, 2011

A new statistical maximum operation for Gaussian mixture models and its evaluations.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

A power grid optimization algorithm considering via reliability.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

An automatic layout method for timing pulse generator of small LCD driver.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

An algorithm to improve accuracy of criticality in statistical static timing analysis.
Proceedings of the Design, Automation and Test in Europe, 2011

2009
A New Statistical Timing Analysis Using Gaussian Mixture Models for Delay and Slew Propagated Together.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Accuracy of the criticality probabilty of a path in statistical timing analysis.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

A new power grid optimization algorithm based on manufacturing cost restriction.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

A Gaussian mixture model for statistical timing analysis.
Proceedings of the 46th Design Automation Conference, 2009

2008
A Power Grid Optimization Algorithm by Observing Timing Error Risk by IR Drop.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

A new statistical timing analyzer propagating delay and slew distributions simultaneously.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
Transistor Sizing of LCD Driver Circuit for Technology Migration.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

2006
An Algorithm to Calculate Correlation Coefficients between Interconnect Delays for Use in Statistical Timing Analysis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

An algorithm for calculating correlation coefficients between Elmore interconnect delays.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Interconnect capacitance extraction for system LCD circuits.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

A design scheme for sampling switch in active matrix LCD.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

2004
Toward stochastic design for digital circuits: statistical static timing analysis.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2002
Parasitic capacitance modeling for multilevel interconnects.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001
A statistical static timing analysis considering correlations between delays.
Proceedings of ASP-DAC 2001, 2001

2000
An interconnect topology optimization by a tree transformation.
Proceedings of ASP-DAC 2000, 2000

1997
Not necessarily more switches more routability [sic.].
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996
Graph based analysis of 2-D FPGA routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

1995
A hybrid hierarchical approach for multi-layer global routing.
Proceedings of the 1995 European Design and Test Conference, 1995

1994
On computational complexity of a detailed routing problem in two dimensional FPGAs.
Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994

1993
An Algorithm to Eliminate All Complex Triangles in a Maximal Planar Graph for Use in VLSI floorplan.
Proceedings of the Algorithmic Aspects of VLSI Layout, 1993

1992
A distributed routing system for multilayer SOG.
Proceedings of the conference on European design automation, 1992

1991
On area-efficient drawings of rectangular duals for VLSI floor-plan.
Math. Program., 1991

1983
On the Layering Problem of Multilayer PWB Wiring.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983

A New Global Router for Gate Array LSIsi.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983

1982
Double-row planar routing and permutation layout.
Networks, 1982

1980
An Algorithm to Enumerate All Cutsets of a Graph in Linear Time per Cutset.
J. ACM, 1980

1977
A New Algorithm for Generating All the Maximal Independent Sets.
SIAM J. Comput., 1977


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