Shuji Tsukiyama

According to our database, Shuji Tsukiyama authored at least 45 papers between 1977 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

Gaussian Mixture Reduction Methods Using Support Vector Machine.

Haruki Kazama, Shuji Tsukiyama

Proceedings of the TENCON 2019, 2019

2017

A New Algorithm to Determine Covariance in Statistical Maximum for Gaussian Mixture Model.

Daiki Azuma, Shuji Tsukiyama

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Approximating the maximum of Gaussians by a Gaussian mixture model for statistical designs.

Daiki Azuma, Shuji Tsukiyama, Masahiro Fukui

Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017

2016

A New Algorithm for Reducing Components of a Gaussian Mixture Model.

Naoya Yokoyama, Daiki Azuma, Shuji Tsukiyama, Masahiro Fukui

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

2015

A statistical method for analyzing lifetime of a series-connected battery cells.

Daisuke Sasaki, Shuji Tsukiyama, Mariko Matsunaga, Junichi Miyamoto, Shingo Takahashi

Proceedings of the 15th International Symposium on Communications and Information Technologies, 2015

2013

A New Delay Distribution Model with a Half Triangular Distribution for Statistical Static Timing Analysis.

Shuji Tsukiyama, Masahiro Fukui

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

An implementation and evaluation of Backward Euler algorithm to GPGPU power grid circuit simulation.

Lei Lin, Masahiro Fukui, Shuji Tsukiyama

Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

A new delay distribution model to take long-term degradation into account.

Shuji Tsukiyama, Masahiro Fukui, Takashi Kambe

Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

Application-specific arithmetic circuit design for a particle tracking application.

Takashi Kambe, Kohsei Takehara, Shuji Tsukiyama

Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

2011

A Statistical Maximum Algorithm for Gaussian Mixture Models Considering the Cumulative Distribution Function Curve.

Shuji Tsukiyama, Masahiro Fukui

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

A power grid optimization algorithm considering timing degradation by NBTI.

Masahiro Fukui, Yoriaki Nagata, Shuji Tsukiyama

Proceedings of the International SoC Design Conference, 2011

A new statistical maximum operation for Gaussian mixture models and its evaluations.

Shuji Tsukiyama, Masahiro Fukui

Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

A power grid optimization algorithm considering via reliability.

Masahiro Fukui, Haruo Miki, Masaya Yoshikawa, Shuji Tsukiyama

Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

An automatic layout method for timing pulse generator of small LCD driver.

Shohei Asakawa, Shuji Tsukiyama, Isao Shirakawa, Shuji Nishi, Tadashi Takeda, Tomoyuki Nagai, Yasushi Kubota

Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

An algorithm to improve accuracy of criticality in statistical static timing analysis.

Shuji Tsukiyama, Masahiro Fukui

Proceedings of the Design, Automation and Test in Europe, 2011

2009

A New Statistical Timing Analysis Using Gaussian Mixture Models for Delay and Slew Propagated Together.

Shingo Takahashi, Shuji Tsukiyama

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Accuracy of the criticality probabilty of a path in statistical timing analysis.

Shuji Tsukiyama, Masahiro Fukui

Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

A new power grid optimization algorithm based on manufacturing cost restriction.

Takayuki Hayashi, Masahiro Fukui, Shuji Tsukiyama

Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

A Gaussian mixture model for statistical timing analysis.

Shingo Takahashi, Yuki Yoshida, Shuji Tsukiyama

Proceedings of the 46th Design Automation Conference, 2009

2008

A Power Grid Optimization Algorithm by Observing Timing Error Risk by IR Drop.

Yoshiyuki Kawakami, Makoto Terao, Masahiro Fukui, Shuji Tsukiyama

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

A new statistical timing analyzer propagating delay and slew distributions simultaneously.

Shingo Takahashi, Shuji Tsukiyama

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007

Transistor Sizing of LCD Driver Circuit for Technology Migration.

Masanori Hashimoto, Takahito Ijichi, Shingo Takahashi, Shuji Tsukiyama, Isao Shirakawa

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

2006

An Algorithm to Calculate Correlation Coefficients between Interconnect Delays for Use in Statistical Timing Analysis.

Shuji Tsukiyama, Masahiko Tomita

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays.

Shingo Takahashi, Shuji Tsukiyama, Masanori Hashimoto, Isao Shirakawa

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

An algorithm for calculating correlation coefficients between Elmore interconnect delays.

Shuji Tsukiyama, Masahiko Tomita

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005

Interconnect capacitance extraction for system LCD circuits.

Yoshihiro Uchida, Sadahiro Tani, Masanori Hashimoto, Shuji Tsukiyama, Isao Shirakawa

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

A design scheme for sampling switch in active matrix LCD.

Shingo Takahashi, Akira Taji, Shuji Tsukiyama, Masanori Hashimoto, Isao Shirakawa

Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

2004

Toward stochastic design for digital circuits: statistical static timing analysis.

Shuji Tsukiyama

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

Parasitic Capacitance Modeling for Non-Planar Interconnects in Liquid Crystal Displays.

Sadahiro Tani, Yoshihiro Uchida, Makoto Furuie, Shuji Tsukiyama, BuYeol Lee, Shuji Nishi, Yasushi Kubota, Isao Shirakawa, Shigeki Imai

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

2002

Parasitic capacitance modeling for multilevel interconnects.

Sadahiro Tani, Yoshihiro Uchida, Makoto Furuie, Shuji Tsukiyama, BuYeol Lee, Shuji Nishi, Yasushi Kubota, Isao Shirakawa, Shigeki Imai

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001

Two-dimensional array layout for NMOS 4-phase dynamic logic.

Makoto Furuie, Takao Onoye, Shuji Tsukiyama, Isao Shirakawa

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

A statistical static timing analysis considering correlations between delays.

Shuji Tsukiyama, Masakazu Tanaka, Masahiro Fukui

Proceedings of ASP-DAC 2001, 2001

2000

An interconnect topology optimization by a tree transformation.

Naofumi Tsujii, Katsutoshi Baba, Shuji Tsukiyama

Proceedings of ASP-DAC 2000, 2000

1997

Not necessarily more switches more routability [sic.].

Yu-Liang Wu, Douglas Chang, Malgorzata Marek-Sadowska, Shuji Tsukiyama

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996

Graph based analysis of 2-D FPGA routing.

Yu-Liang Wu, Shuji Tsukiyama, Malgorzata Marek-Sadowska

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

1995

A hybrid hierarchical approach for multi-layer global routing.

Masayuki Hayashi, Shuji Tsukiyama

Proceedings of the 1995 European Design and Test Conference, 1995

1994

On computational complexity of a detailed routing problem in two dimensional FPGAs.

Yu-Liang Wu, Shuji Tsukiyama, Malgorzata Marek-Sadowska

Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994

1993

An Algorithm to Eliminate All Complex Triangles in a Maximal Planar Graph for Use in VLSI floorplan.

Shuji Tsukiyama, Keiichi Koike, Isao Shirakawa

Proceedings of the Algorithmic Aspects of VLSI Layout, 1993

1992

A distributed routing system for multilayer SOG.

Takashi Shimamoto, Hidetaka Hane, Isao Shirakawa, Shuji Tsukiyama, Shoji Shinoda, Nobuyasu Yui, Nobuyuki Nishiguchi

Proceedings of the conference on European design automation, 1992

1991

On area-efficient drawings of rectangular duals for VLSI floor-plan.

Katsunori Tani, Shuji Tsukiyama, Shoji Shinoda, Isao Shirakawa

Math. Program., 1991

1983

On the Layering Problem of Multilayer PWB Wiring.

Shuji Tsukiyama, Ernest S. Kuh, Isao Shirakawa

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983

A New Global Router for Gate Array LSIsi.

Shuji Tsukiyama, Ikuo Harada, Masahiro Fukui, Isao Shirakawa

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983

1982

Double-row planar routing and permutation layout.

Shuji Tsukiyama, Ernest S. Kuh

Networks, 1982

1980

An Algorithm to Enumerate All Cutsets of a Graph in Linear Time per Cutset.

Shuji Tsukiyama, Isao Shirakawa, Hiroshi Ozaki, Hiromu Ariyoshi

J. ACM, 1980

1977

A New Algorithm for Generating All the Maximal Independent Sets.

Shuji Tsukiyama, Mikio Ide, Hiromu Ariyoshi, Isao Shirakawa

SIAM J. Comput., 1977