Akira Onozawa

According to our database1, Akira Onozawa authored at least 19 papers between 1990 and 2012.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2012
An Image Recognition System for Multiple Video Inputs over a Multi-FPGA System.
Proceedings of the IEEE 6th International Symposium on Embedded Multicore/Manycore SoCs, 2012

A novel BMNoC configuration algorithm utilizing communication volume and locality among cores.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A novel hardware algorithm for real-time image recognition based on real AdaBoost classification.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A hybrid NoC architecture utilizing packet transmission priority control method.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011
A heuristic algorithm for reducing system-level test vectors with high branch coverage.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2004
Arm-Pointer: 3D Pointing Interface for Real-World Interaction.
Proceedings of the Computer Vision in Human-Computer Interaction, 2004

2003
A Mirror Metaphor Interaction System: Touching Remote Real Objects in an Augmented Reality Environment.
Proceedings of the 2003 IEEE / ACM International Symposium on Mixed and Augmented Reality (ISMAR 2003), 2003

2002
Representation of Pseudo Inter-reflection and Transparency by Considering Characteristics of Human Vision.
Comput. Graph. Forum, 2002

Regeneration of real objects in the real world.
Proceedings of the 29th International Conference on Computer Graphics and Interactive Techniques, 2002

Hexagonal Image Representation for 3-D Photorealistic Reconstruction.
Proceedings of the 16th International Conference on Pattern Recognition, 2002

2001
Personal Information Market: Toward a Secure and Efficient Trade of Privacy.
Proceedings of the Human Society and the Internet, 2001

1999
A 557-mW, 2.5-Gbit/s SONET/SDH regenerator-section terminating LSI chip using low-power bipolar-LSI design.
IEEE J. Solid State Circuits, 1999

1998
High-speed, low-power, bipolar standard cell design methodology for Gbit/s signal processing.
IEEE J. Solid State Circuits, 1998

1997
An Efficient Paired-net Routing Algorithm for High-speed Bipolar LSIs.
Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

1996
A Balanced-Mesh Clock Routing Technique Using Circuit Partitioning.
Proceedings of the 1996 European Design and Test Conference, 1996

1995
Performance driven spacing algorithms using attractive and repulsive constraints for submicron LSI's.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Post-layout optimization of power and timing for ECL LSIs.
Proceedings of the 1995 European Design and Test Conference, 1995

1993
A spacing algorithm for performance enhancement and cross-talk reduction.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1990
Layout Compaction with Attractive and Repulsive Constraints.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990


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