Khawar Sarfraz

According to our database, Khawar Sarfraz authored at least 9 papers between 2011 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

8.5 A Scalable Adaptive ADC/DSP-Based 1.25-to-56Gbps/112Gbps High-Speed Transceiver Architecture Using Decision-Directed MMSE CDR in 16nm and 7nm.

Danfeng Xu, Yu Kou, Paul Lai, Zichuan Cheng, Tze Yin Cheung, Larry Moser, Yang Zhang, Xiaolong Liu, Man Pio Lam, Haikun Jia, Quan Pan, Wing Hong Szeto, Chi Fai Tang, Ka Fai Mak, Khawar Sarfraz, Tairan Zhu, Ming Kwan, Emily Yim Lee Au, Cormac Conroy, Kai-Keung Chan

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2017

A 1.2V-to-0.4V 3.2GHz-to-14.3MHz Power-Efficient 3-Port Register File in 65-nm CMOS.

Khawar Sarfraz, Mansun Chan

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

A 140-mV Variation-Tolerant Deep Sub-Threshold SRAM in 65-nm CMOS.

Khawar Sarfraz, Jin He, Mansun Chan

IEEE J. Solid State Circuits, 2017

2016

A compact low-power 4-port register file with grounded write bitlines and single-ended read operations.

Khawar Sarfraz, Mansun Chan

Integr., 2016

A voltage-scalable zero-delay-overhead scheme for standby power reduction in dynamic register files.

Khawar Sarfraz, Mansun Chan

Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

2015

A 65nm 3.2GHz 44.2mW Low-Vt register file with robust low-capacitance dynamic local bitlines.

Khawar Sarfraz, Mansun Chan

Proceedings of the ESSCIRC Conference 2015, 2015

Nanoscale register file circuit design - Challenges and opportunities.

Khawar Sarfraz, Mansun Chan

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2013

Characterization of a low leakage current and high-speed 7T SRAM circuit with wide voltage margins.

Khawar Sarfraz, Volkan Kursun

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

2011

A novel low-leakage 8T differential SRAM cell.

Khawar Sarfraz

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011