Haikun Jia

Orcid: 0000-0003-4564-8938

According to our database1, Haikun Jia authored at least 64 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
A Low-Phase-Noise VCO With Common-Mode Resonance Expansion and Intrinsic Differential 2nd-Harmonic Output Based on a Single Three-Coil Transformer.
IEEE J. Solid State Circuits, January, 2024

19.5 A 13.7-to-41.5GHz 214.1dBc/Hz FoMT Quad-Core Quad-Mode VCO Using an Oscillation-Mode-Splitting Technique.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023
A 24-30-GHz Four-Element Phased Array Transceiver With Low Insertion Loss Compact T/R Switch and Bidirectional Phase Shifter for 5G Communication.
IEEE Trans. Very Large Scale Integr. Syst., November, 2023

A Compact and Low Phase Noise Square-Geometry Quad-Core Class-F VCO Using Parallel Inductor-Sharing Technique.
IEEE J. Solid State Circuits, October, 2023

A 128 Gbps PAM-4 feed forward equaliser with optimized 1UI pulse generator in 65 nm CMOS.
IET Circuits Devices Syst., May, 2023

A Low-Phase-Noise Quad-Core Millimeter-Wave Fundamental VCO Using Circular Triple-Coupled Transformer in 65-nm CMOS.
IEEE J. Solid State Circuits, February, 2023

A D-Band Joint Radar-Communication CMOS Transceiver.
IEEE J. Solid State Circuits, February, 2023

An 11.4-to-16.4GHz FMCW Digital PLL with Cycle-slipping Compensation and Back-tracking DPD Achieving 0.034% RMS Frequency Error under 3.4-GHz Chirp Bandwidth and 960-MHz/μs Chirp Slope.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

A 10-to-300MHz Fractional Output Divider with -80dBc Worst-Case Fractional Spurs Using Auxiliary-PLL-Based Background 0th/1<sup>st</sup>/2<sup>nd</sup>-Order DTC INL Calibration.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

An 11.5-to-14.3GHz 192.8dBc/Hz FoM at 1MHz Offset Dual-Core Enhanced Class-F VCO with Common-Mode-Noise Self-Cancellation and Isolation Technique.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A 6.5-to-8GHz IEEE 802.15.4z-compliant All-Digital UWB Transmitter with Integrated Fast-Settling Master-Slave Regulator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

INVITED PAPER: A 312.5Mbps-32Gbps JESD204C Wireline Transceiver Back-Compatible with JESD204B in 28nm CMOS.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023

A 4.8-GHz Time-Interleaved Multi-Reference PLL with 16.1-fs Jitter.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

A 37-to-41.8 GHz Double-Gm-Boosting LNA with 2.9-dB NFmin Using Quadruple-Coupling Transformer for Phased-Array Transceivers.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

Transceiver SoC for Wireless Indoor Sensing Data-fusion.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

A 100 MHz-Reference, 10.3-to-11.1 GHz Quadrature PLL with 33.7-fsrms Jitter and -83.9 dBc Reference Spur Level using a -130.8 dBc/Hz Phase Noise at 1MHz offset Folded Series-Resonance VCO in 65nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

A 25.0-to-35.9GHz Dual-Layer Quad-Core Dual-Mode VCO with 189.1dBc/Hz FoM and 200.2dBc/Hz FoMT at 1MHz Offset in 65nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

A Transient Enhancement Digital LDO with Adaptive Ripple Cancelation Based on Optimal Compensation Period Approximation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

IEEE ASSCC 2023/ Session 10/ Paper 10.5.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

A 26.9-GHz 4-Element Code-Domain Hybrid Beamforming Phased-Array Receiver.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

A 27-to-31.6 GHz 8-Element Phased-Array Transmitter Front-End with Inter-Element-Interference Cancellation Scheme in 65 nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

A 4-Element 4-Beam Ka-Band Phased-Array Receiver Using Mesh Topology in 65 nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

A Compact E-Band Load-Modulation Balanced Power Amplifier Using Coupled Transmission-Line Output Network Achieving 22.1-dBm Psat and 34.9%/12.2% Efficiency at Psat/6-dB PBO.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

A Fully Integrated Bit-to-Bit 24/48Gb/s QPSK/16-QAM D-Band Transceiver with Mixed-Signal Baseband in 28nm CMOS Technology.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

2022
A 4.4-GHz 193.2-dB FoM 8-Shaped-Inductor Based LC-VCO Using Orthogonal-Coupled Triple-Coil Transformer.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A Self-Adapted Two-Point Modulation Type-II Digital PLL for Fast Chirp Rate and Wide Chirp-Bandwidth FMCW Signal Generation.
IEEE J. Solid State Circuits, 2022

A 53.6-to-60.2GHz Many-Core Fundamental Oscillator With Scalable Mesh Topology Achieving -136.0dBc/Hz Phase Noise at 10MHz Offset and 190.3dBc/Hz Peak FoM in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

A Highly Linearized Ka-band Heterodyne Receiver using a Folded Class-AB Inductive Peaking Mixer and Magnetic-Self-Cancellation-Transformer-Based IF Amplifiers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A 56Gb/s De-serializer with PAM-4 CDR for Chiplet Optical-I/O.
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022

A 22.8 GHz to 32.8 GHz Compact Power Amplifier with a 15 dBm Output P1dB and 36.5% Peak PAE in 65-nm CMOS.
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022

A 4.7GHz Synchronized-Multi-Reference PLL with In-Band Phase Noise Lower than Reference Phase Noise +20logN<sub>div</sub>.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

A 12.5-to-15.4GHz, -118.9dBc/Hz PN at 1MHz offset, and 191.0dBc/Hz FoM VCO with Common-Mode Resonance Expansion and Simultaneous Differential 2ND-Harmonic Output using a Single Three-Coil Transformer in 65nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

A 76-81 GHz FMCW 2TX/3RX Radar Transceiver with Integrated Mixed-Mode PLL and Series-Fed Patch Antenna Array.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021
A 122-168GHz Radar/Communication Fusion-Mode Transceiver with 30GHz Chirp Bandwidth, 13dBm Psat, and 8.3dBm OP1dB in 28nm CMOS.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

A 11.1-to-14.2 GHz Self-adapted Two-point Modulation Dual-path Type-II Digital PLL Concurrently Achieving 124.7-MHz/μs Chirp Rate and 2.27-GHz Bandwidth.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

8.5 A Scalable Adaptive ADC/DSP-Based 1.25-to-56Gbps/112Gbps High-Speed Transceiver Architecture Using Decision-Directed MMSE CDR in 16nm and 7nm.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

A 60GHz 186.5dBc/Hz FoM Quad-Core Fundamental VCO Using Circular Triple-Coupled Transformer with No Mode Ambiguity in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

A C-band FMCW Radar Transmitter with a 22 dBm Output Power Series-stacking CMCD PA for Long-distance Detection in 180-nm CMOS Technology.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

Optimization methods for high inductance-density inductors for high speed integrated circuits.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

An Ultra-Compact 16-to-45 GHz Power Amplifier within A Single Inductor Footprint Using Folded Transformer Technique.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

An 8.2-to-21.5 GHz Dual-Core Quad-Mode Orthogonal-Coupled VCO with Concurrently Dual-Output using Parallel 8-Shaped Resonator.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

A 24-30GHz 4-Element Phased Array Transceiver with Low Insertion Loss Compact T/R Switch and Bidirectional Phase Shifter in 65 nm CMOS Technology.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

A 33.5-37.5 GHz 4-Element Phased-Array Transceiver Front-End with High-Accuracy Low-Variation 6-bit Resolution 360° Phase Shift and 0~31.5 dB Gain Control in 65 nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

A Highly Integrated Energy-efficient CMOS Millimeter-wave Transceiver with Direct-modulation Digital Transmitter, Quadrature Phased-coupled Frequency Synthesizer and Substrate-Integrated Waveguide E-shaped Patch Antenna.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
A 35-GHz TX and RX Front End With High TX Output Power for Ka-Band FMCW Phased-Array Radar Transceivers in CMOS Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2020

A U-Band PLL Using Implicit Distributed Resonators for Sub-THz Wireless Transceivers in 40 nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A 27-31 ​GHz 6-bit phase shifter with low phase error/gain variation in 65 ​nm CMOS.
Microelectron. J., 2020

An Energy-Efficient 10-Gb/s CMOS Millimeter-Wave Transceiver With Direct-Modulation Digital Transmitter and I/Q Phase-Coupled Frequency Synthesizer.
IEEE J. Solid State Circuits, 2020

A 53.1-to-64.5 GHz In-Phase Coupled Quadrature Injection-Locked Oscillator with Transformer-Based I/Q-Phase Differential Injection Scheme.
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020

A 44-52 GHz Reflection-type Phase Shifter with 1.4° Phase Resolution in 28nm CMOS Process.
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020

2019
International Solid-State Circuits Conference 2019 aims at "envisioning the future".
Sci. China Inf. Sci., 2019

2018
A Full Ka-Band Power Amplifier With 32.9% PAE and 15.3-dBm Power in 65-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

2017
An 80-83 GHz CMOS DCO based on DiCAD technique for size, linearity and noise optimization.
Sci. China Inf. Sci., 2017

2016
A 77 GHz Frequency Doubling Two-Path Phased-Array FMCW Transceiver for Automotive Radar.
IEEE J. Solid State Circuits, 2016

Simple and robust self-healing technique for millimetre-wave amplifiers.
IET Circuits Devices Syst., 2016

A 32.9% PAE, 15.3 dBm, 21.6-41.6 GHz power amplifier in 65nm CMOS using coupled resonators.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
A 60-GHz CMOS Dual-Mode Power Amplifier With Efficiency Enhancement at Low Output Power.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

25.6 A 70.5-to-85.5GHz 65nm phase-locked loop with passive scaling of loop filter.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

An 8.2 GHz triple coupling low-phase-noise class-F QVCO in 65nm CMOS.
Proceedings of the ESSCIRC Conference 2015, 2015

A frequency doubling two-path phased-array FMCW radar transceiver in 65nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

A 60-GHz wireless transceiver with dual-mode power amplifier for IEEE 802.11ad in 65nm CMOS.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
A 38- to 40-GHz Current-Reused Active Phase Shifter Based on the Coupled Resonator.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

A 77 GHz FMCW radar transmitter with reconfigurable power amplifier in 65 nm CMOS.
Microelectron. J., 2014

2012
A 1 V, 69-73 GHz CMOS power amplifier based on improved Wilkinson power combiner.
Microelectron. J., 2012


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