Volkan Kursun
Orcid: 0000000280501774
According to our database^{1},
Volkan Kursun
authored at least 115 papers
between 2002 and 2022.
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Bibliography
2022
Impact of Sheet Width and Silicon Height in 3D Stacked Nanosheet GAA Transistor Technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
Integr., 2021
Optimization of 3D Stacked Nanosheets in 5nm Gateallaround Transistor Technology.
Proceedings of the 34th IEEE International SystemonChip Conference, 2021
2020
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
Proceedings of the 29th International Symposium on Power and Timing Modeling, 2019
Statistical Modeling and Design of a 16nm 9T SRAM Cell Considering PostSynthesis Removal of Metallic CarbonNanotubes.
Proceedings of the International Conference on Electronics, Information, and Communication, 2019
CarbonBased ThreeDimensional SRAM Cell with Minimum InterLayer Area Skew Considering Process imperfections.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
2017
Variable strength keeper for highspeed and lowleakage carbon nanotube domino logic.
Microelectron. J., 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2016
Microelectron. J., 2016
Write Assist SRAM Cell with Asymmetrical Bitline Access Transistors for Enhanced Data Stability and Write Ability.
J. Circuits Syst. Comput., 2016
Variabilityaware 7T SRAM circuit with low leakage high data stability SLEEP mode.
Integr., 2016
Proceedings of the 22nd IEEE International Symposium on OnLine Testing and Robust System Design, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
2Phase highfrequency clock distribution with SPLITIO dualVt repeaters for suppressed leakage currents.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Carbonbased sleep switch dynamic logic circuits with variable strength keeper for lowerleakage currents and higherspeed.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
Novel LowLeakage and HighSpeed TripleThresholdVoltage Buffers With Skewed Inputs and Outputs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
A Comprehensive Comparison of Data Stability Enhancement Techniques With Novel Nanoscale SRAM Cells Under Parameter Fluctuations.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Mode transition timing and energy overhead analysis in noiseaware MTCMOS circuits.
Microelectron. J., 2014
Highspeed and lowleakage FinFET SRAM cell with enhanced read and write voltage margins.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
A comprehensive comparison of superior triplethresholdvoltage 7transistor, 8transistor, and 9transistor SRAM cells.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Triplethresholdvoltage 9transistor SRAM cell for data stability and energyefficiency at ultralow power supply voltages.
Proceedings of the 26th International Conference on Microelectronics, 2014
Proceedings of the 26th International Conference on Microelectronics, 2014
2013
Reactivation Noise Suppression With Sleep Signal Slew Rate Modulation in MTCMOS Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2013
Characterization of mode transition timing overhead for net energy savings in lownoise MTCMOS circuits.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and SystemonChip, 2013
Characterization of a low leakage current and highspeed 7T SRAM circuit with wide voltage margins.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
Impact of process parameter and supply voltage fluctuations on multithresholdvoltage seventransistor static memory cells.
Proceedings of the International Symposium on Quality Electronic Design, 2013
A novel 6T SRAM cell with asymmetrically gate underlap engineered FinFETs for enhanced read data stability and write ability.
Proceedings of the International Symposium on Quality Electronic Design, 2013
Novel dualthresholdvoltage energyefficient buffers for driving large extrinsic load capacitance.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Lowpower and compact NP dynamic CMOS adder with 16nm carbon nanotube transistors.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Lowleakage hybrid FinFET SRAM cell with asymmetrical gate overlap / underlap bitline access transistors for enhanced read data stability.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Underlap engineered eighttransistor SRAM cell for stronger data stability enhanced write ability and suppressed leakage power consumption.
Proceedings of the 20th IEEE International Conference on Electronics, 2013
2012
Threshold Voltage Tuning for Faster Activation With Lower Noise in TriMode MTCMOS Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2012
Proceedings of the International SoC Design Conference, 2012
Multiphase sleep signal modulation for mode transition noise mitigation in MTCMOS circuits.
Proceedings of the International SoC Design Conference, 2012
Fullcustom design of low leakage data preserving ground gated 6T SRAM cells to facilitate singleended write operations.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
Ground Bouncing Noise Suppression Techniques for Data Preserving Sequential MTCMOS Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2011
NoiseAware Data Preserving Sequential MTCMOS Circuits with Dynamic Forward Body Bias.
J. Circuits Syst. Comput., 2011
Uniform carbon nanotube diameter and nanoarray pitch for VLSI of 16nm Pchannel MOSFETs.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and SystemonChip, 2011
Sleep signal slew rate modulation for mode transition noise suppression in ground gated integrated circuits.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011
Symmetrical triplethresholdvoltage ninetransistor SRAM circuit with superior noise immunity and overall electrical quality.
Proceedings of the International SoC Design Conference, 2011
Leakage current and bottom gate voltage considerations in developing maximum performance 16nm Nchannel carbon nanotube transistors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2010
Dual Supply Voltages and Dual Clock Frequencies for Lower Clock Power and Suppressed TemperatureGradientInduced Clock Skew.
IEEE Trans. Very Large Scale Integr. Syst., 2010
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
J. Low Power Electron., 2010
Trimode Operation for Noise Reduction and Data Preservation in LowLeakage MultiThreshold CMOS Circuits.
Proceedings of the VLSISoC: ForwardLooking Trends in IC and Systems Design, 2010
Reactivation noise suppression with threshold voltage tuning in sequential MTCMOS circuits.
Proceedings of the 18th IEEE/IFIP VLSISoC 2010, 2010
Smooth awakenings: Reactivation noise suppressed lowleakage and robust MTCMOS flipflops.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
Microelectron. J., 2009
Temperatureadaptive voltage scaling for enhanced energy efficiency in subthreshold memory arrays.
Microelectron. J., 2009
Robust FinFET Memory Circuits with PType Data Access Transistors for Higher Integration Density and Reduced Leakage Power.
J. Low Power Electron., 2009
2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
Temperatureadaptive voltage tuning for enhanced energy efficiency in ultralowvoltage circuits.
Microelectron. J., 2008
Clock Distribution Networks with Gradual Signal Transition Time Relaxation for Reduced Power Consumption.
J. Circuits Syst. Comput., 2008
Technique for Accurate Power and Energy Measurement with the ComputerAided Design Tools.
J. Circuits Syst. Comput., 2008
TemperatureAdaptive Energy Reduction Techniques for NanoCMOS Circuits Displaying Reversed temperature Dependence.
J. Circuits Syst. Comput., 2008
Compact FinFET Memory Circuits with PType Data Access Transistors for Low Leakage and Robust Operation.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Characterization of New Static IndependentGateBiased FinFET Latches and FlipFlops under Process Variations.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Statistical Data Stability and Leakage Evaluation of FinFET SRAM Cells with Dynamic Threshold Voltage Tuning under Process Parameter Fluctuations.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Workfunction engineering for reduced power and higher integration density: An alternative to sizing for stability in FinFET memory circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Asymmetric dualgate multifin keeper bias options and optimization for low power and robust FinFET domino logic.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
MultiVth FinFET sequential circuits with independentgate bias and workfunction engineering for reduced power consumption.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2007
PMOSOnly Sleep Switch DualThreshold Voltage Domino Logic in Sub65nm CMOS Technologies.
IEEE Trans. Very Large Scale Integr. Syst., 2007
Voltage optimization for simultaneous energy efficiency and temperature variation resilience in CMOS circuits.
Microelectron. J., 2007
Proceedings of the 2007 IEEE International SOC Conference, 2007
An independentgate FinFET SRAM cell for high data stability and enhanced integration density.
Proceedings of the 2007 IEEE International SOC Conference, 2007
DualV_DD Clock Distribution for Low Power and Minimum Temperature Fluctuations Induced Skew.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Dual signal frequencies and voltage levels for low power and temperaturegradient tolerant clock distribution.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Buffer Insertion and Sizing in Clock Distribution Networks with Gradual Transition Time Relaxation for Reduced Power Consumption.
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Low Power and Stable FinFET SRAM with Static Independent Gate Bias for Enhanced Integration Density.
Proceedings of the 14th IEEE International Conference on Electronics, 2007
New MTCMOS FlipFlops with Simple Control Circuitry and Low Leakage Data Retention Capability.
Proceedings of the 14th IEEE International Conference on Electronics, 2007
TemperatureAdaptive Energy Reduction for UltraLow PowerSupplyVoltage Subthreshold Logic Circuits.
Proceedings of the 14th IEEE International Conference on Electronics, 2007
2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
Reversed TemperatureDependent Propagation Delay Characteristics in Nanometer CMOS Circuits.
IEEE Trans. Circuits Syst. II Express Briefs, 2006
Sleep switch dual threshold voltage domino logic with reduced subthreshold and gate oxide leakage current.
Microelectron. J., 2006
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006
Supply and Threshold Voltage Optimization for Temperature Variation Insensitive Circuit Performance: A Comparison.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006
High Speed Low Swing Dynamic Circuits with Multiple Supply and Threshold Voltages.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Robust Dynamic Node Low Voltage Swing Domino Logic with Multiple Threshold Voltages.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Wide temperature spectrum low leakage dynamic circuit technique for sub65nm CMOS technologies.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Impact of temperature fluctuations on circuit characteristics in 180nm and 65nm CMOS technologies.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006
2005
Microelectron. J., 2005
Shifted Leakage Power Characteristics of Dynamic Circuits Due to Gate Oxide Tunneling.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005
Cascode buffer for monolithic voltage conversion operating at high input supply voltages.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2004
Sleep switch dual threshold Voltage domino logic with reduced standby leakage current.
IEEE Trans. Very Large Scale Integr. Syst., 2004
IEEE Trans. Circuits Syst. II Express Briefs, 2004
High Input Voltage StepDown DCDC Converters for Integration in a Low Voltage CMOS Process.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004
Node Voltage Dependent Subthreshold Leakage Current Characteristics of Dynamic Circuits.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004
Feasibility of monolithic and 3Dstacked DCDC converters for microprocessors in 90nm technology generation.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004
Forward body biased keeper for enhanced noise immunity in domino logic circuits.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Energy efficient dual threshold voltage dynamic circuits employing sleep switches to minimize subthreshold leakage.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2003
Analysis of buck converters for onchip integration with a dual supply voltage microprocessor.
IEEE Trans. Very Large Scale Integr. Syst., 2003
IEEE Trans. Very Large Scale Integr. Syst., 2003
Computer, 2003
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003
2002
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002