Volkan Kursun

Orcid: 0000-0002-8050-1774

According to our database1, Volkan Kursun authored at least 115 papers between 2002 and 2022.

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Bibliography

2022
Impact of Sheet Width and Silicon Height in 3D Stacked Nanosheet GAA Transistor Technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
Novel low leakage and energy efficient dual-pullup/dual-pulldown repeater.
Integr., 2021

Optimization of 3D Stacked Nanosheets in 5nm Gate-all-around Transistor Technology.
Proceedings of the 34th IEEE International System-on-Chip Conference, 2021

2020
Monolithic 3D Carbon Nanotube Memory for Enhanced Yield and Integration Density.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

2019
Low Leakage Clock Tree With Dual-Threshold- Voltage Split Input-Output Repeaters.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Energy Efficient Clock Distribution with Low-Leakage Multi-Vt Buffers.
Proceedings of the 29th International Symposium on Power and Timing Modeling, 2019

Statistical Modeling and Design of a 16nm 9T SRAM Cell Considering Post-Synthesis Removal of Metallic Carbon-Nanotubes.
Proceedings of the International Conference on Electronics, Information, and Communication, 2019

Carbon-Based Three-Dimensional SRAM Cell with Minimum Inter-Layer Area Skew Considering Process imperfections.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2017
Variable strength keeper for high-speed and low-leakage carbon nanotube domino logic.
Microelectron. J., 2017

Metallic-carbon-nanotube-removal tolerant SRAM cell with 9 transistors.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
Low power and robust memory circuits with asymmetrical ground gating.
Microelectron. J., 2016

Write Assist SRAM Cell with Asymmetrical Bitline Access Transistors for Enhanced Data Stability and Write Ability.
J. Circuits Syst. Comput., 2016

Variability-aware 7T SRAM circuit with low leakage high data stability SLEEP mode.
Integr., 2016

Variations-tolerant 9T SRAM circuit with robust and low leakage SLEEP mode.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

2015
A Novel Robust and Low-Leakage SRAM Cell With Nine Carbon Nanotube Transistors.
IEEE Trans. Very Large Scale Integr. Syst., 2015

2-Phase high-frequency clock distribution with SPLIT-IO dual-Vt repeaters for suppressed leakage currents.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Carbon-based sleep switch dynamic logic circuits with variable strength keeper for lower-leakage currents and higher-speed.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
Novel Low-Leakage and High-Speed Triple-Threshold-Voltage Buffers With Skewed Inputs and Outputs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A Comprehensive Comparison of Data Stability Enhancement Techniques With Novel Nanoscale SRAM Cells Under Parameter Fluctuations.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Carbon Nanotubes Blowing New Life Into NP Dynamic CMOS Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Mode transition timing and energy overhead analysis in noise-aware MTCMOS circuits.
Microelectron. J., 2014

High-speed and low-leakage FinFET SRAM cell with enhanced read and write voltage margins.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

A comprehensive comparison of superior triple-threshold-voltage 7-transistor, 8-transistor, and 9-transistor SRAM cells.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Triple-threshold-voltage 9-transistor SRAM cell for data stability and energy-efficiency at ultra-low power supply voltages.
Proceedings of the 26th International Conference on Microelectronics, 2014

Low-leakage 9-CN-MOSFET SRAM cell with enhanced read and write voltage margins.
Proceedings of the 26th International Conference on Microelectronics, 2014

2013
Reactivation Noise Suppression With Sleep Signal Slew Rate Modulation in MTCMOS Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Characterization of mode transition timing overhead for net energy savings in low-noise MTCMOS circuits.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Characterization of a low leakage current and high-speed 7T SRAM circuit with wide voltage margins.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Ground gated 8T SRAM cells with enhanced read and hold data stability.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Impact of process parameter and supply voltage fluctuations on multi-threshold-voltage seven-transistor static memory cells.
Proceedings of the International Symposium on Quality Electronic Design, 2013

A novel 6T SRAM cell with asymmetrically gate underlap engineered FinFETs for enhanced read data stability and write ability.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Novel dual-threshold-voltage energy-efficient buffers for driving large extrinsic load capacitance.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Low-power and compact NP dynamic CMOS adder with 16nm carbon nanotube transistors.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Low-leakage hybrid FinFET SRAM cell with asymmetrical gate overlap / underlap bitline access transistors for enhanced read data stability.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Underlap engineered eight-transistor SRAM cell for stronger data stability enhanced write ability and suppressed leakage power consumption.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

2012
Threshold Voltage Tuning for Faster Activation With Lower Noise in Tri-Mode MTCMOS Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2012

NP dynamic CMOS resurrection with carbon nanotube field effect transistors.
Proceedings of the International SoC Design Conference, 2012

Multi-phase sleep signal modulation for mode transition noise mitigation in MTCMOS circuits.
Proceedings of the International SoC Design Conference, 2012

Full-custom design of low leakage data preserving ground gated 6T SRAM cells to facilitate single-ended write operations.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
Multi-Threshold Voltage FinFET Sequential Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Ground Bouncing Noise Suppression Techniques for Data Preserving Sequential MTCMOS Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Noise-Aware Data Preserving Sequential MTCMOS Circuits with Dynamic Forward Body Bias.
J. Circuits Syst. Comput., 2011

Uniform carbon nanotube diameter and nanoarray pitch for VLSI of 16nm P-channel MOSFETs.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Sleep signal slew rate modulation for mode transition noise suppression in ground gated integrated circuits.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

Symmetrical triple-threshold-voltage nine-transistor SRAM circuit with superior noise immunity and overall electrical quality.
Proceedings of the International SoC Design Conference, 2011

Leakage current and bottom gate voltage considerations in developing maximum performance 16nm N-channel carbon nanotube transistors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
Dual Supply Voltages and Dual Clock Frequencies for Lower Clock Power and Suppressed Temperature-Gradient-Induced Clock Skew.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Ground-Bouncing-Noise-Aware Combinational MTCMOS Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Low-Leakage and Compact Registers with Easy-Sleep Mode.
J. Low Power Electron., 2010

Tri-mode Operation for Noise Reduction and Data Preservation in Low-Leakage Multi-Threshold CMOS Circuits.
Proceedings of the VLSI-SoC: Forward-Looking Trends in IC and Systems Design, 2010

Reactivation noise suppression with threshold voltage tuning in sequential MTCMOS circuits.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Smooth awakenings: Reactivation noise suppressed low-leakage and robust MTCMOS flip-flops.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Low Power and High Speed Multi Threshold Voltage Interface Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2009

FinFET domino logic with independent gate keepers.
Microelectron. J., 2009

Temperature-adaptive voltage scaling for enhanced energy efficiency in subthreshold memory arrays.
Microelectron. J., 2009

Robust FinFET Memory Circuits with P-Type Data Access Transistors for Higher Integration Density and Reduced Leakage Power.
J. Low Power Electron., 2009

2008
Characterization of a Novel Nine-Transistor SRAM Cell.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Temperature-adaptive voltage tuning for enhanced energy efficiency in ultra-low-voltage circuits.
Microelectron. J., 2008

Clock Distribution Networks with Gradual Signal Transition Time Relaxation for Reduced Power Consumption.
J. Circuits Syst. Comput., 2008

Technique for Accurate Power and Energy Measurement with the Computer-Aided Design Tools.
J. Circuits Syst. Comput., 2008

Temperature-Adaptive Energy Reduction Techniques for Nano-CMOS Circuits Displaying Reversed temperature Dependence.
J. Circuits Syst. Comput., 2008

Compact FinFET Memory Circuits with P-Type Data Access Transistors for Low Leakage and Robust Operation.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Characterization of New Static Independent-Gate-Biased FinFET Latches and Flip-Flops under Process Variations.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Statistical Data Stability and Leakage Evaluation of FinFET SRAM Cells with Dynamic Threshold Voltage Tuning under Process Parameter Fluctuations.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Dynamic wordline voltage swing for low leakage and stable static memory banks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Low power and robust 7T dual-Vt SRAM circuit.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Work-function engineering for reduced power and higher integration density: An alternative to sizing for stability in FinFET memory circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Asymmetric dual-gate multi-fin keeper bias options and optimization for low power and robust FinFET domino logic.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

Multi-Vth FinFET sequential circuits with independent-gate bias and work-function engineering for reduced power consumption.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
PMOS-Only Sleep Switch Dual-Threshold Voltage Domino Logic in Sub-65-nm CMOS Technologies.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Voltage optimization for simultaneous energy efficiency and temperature variation resilience in CMOS circuits.
Microelectron. J., 2007

Low-power high-performance FinFET sequential circuits.
Proceedings of the 2007 IEEE International SOC Conference, 2007

An independent-gate FinFET SRAM cell for high data stability and enhanced integration density.
Proceedings of the 2007 IEEE International SOC Conference, 2007

Dual-V_DD Clock Distribution for Low Power and Minimum Temperature Fluctuations Induced Skew.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Charge Recycling Between Virtual Power and Ground Lines for Low Energy MTCMOS.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distribution.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Multi-Vth Level Conversion Circuits for Multi-VDD Systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Low-Power Low-Voltage Hot-Spot Tolerant Clocking with Suppressed Skew.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

High Read Stability and Low Leakage Cache Memory Cell.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Charge Recycling MTCMOS for Low Energy Active/Sleep Mode Transitions.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Leakage-Aware Design of Nanometer SoC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Buffer Insertion and Sizing in Clock Distribution Networks with Gradual Transition Time Relaxation for Reduced Power Consumption.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

Low Power and Stable FinFET SRAM with Static Independent Gate Bias for Enhanced Integration Density.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

New MTCMOS Flip-Flops with Simple Control Circuitry and Low Leakage Data Retention Capability.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

Temperature-Adaptive Energy Reduction for Ultra-Low Power-Supply-Voltage Subthreshold Logic Circuits.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006
Leakage Biased pMOS Sleep Switch Dynamic Circuits.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

Leakage Power Characteristics of Dynamic Circuits in Nanometer CMOS Technologies.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

Reversed Temperature-Dependent Propagation Delay Characteristics in Nanometer CMOS Circuits.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

Sleep switch dual threshold voltage domino logic with reduced subthreshold and gate oxide leakage current.
Microelectron. J., 2006

High Read Stability and Low Leakage SRAM Cell Based on Data/Bitline Decoupling.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Supply and Threshold Voltage Optimization for Temperature Variation Insensitive Circuit Performance: A Comparison.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

High Speed Low Swing Dynamic Circuits with Multiple Supply and Threshold Voltages.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Leakage Biased Sleep Switch Domino Logic.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Robust Dynamic Node Low Voltage Swing Domino Logic with Multiple Threshold Voltages.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Wide temperature spectrum low leakage dynamic circuit technique for sub-65nm CMOS technologies.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Impact of temperature fluctuations on circuit characteristics in 180nm and 65nm CMOS technologies.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Leakage current starved domino logic.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

A design methodology for temperature variation insensitive low power circuits.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

2005
Monolithic voltage conversion in low-voltage CMOS technologies.
Microelectron. J., 2005

Shifted Leakage Power Characteristics of Dynamic Circuits Due to Gate Oxide Tunneling.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

Cascode buffer for monolithic voltage conversion operating at high input supply voltages.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Sleep switch dual threshold Voltage domino logic with reduced standby leakage current.
IEEE Trans. Very Large Scale Integr. Syst., 2004

Low-voltage-swing monolithic dc-dc conversion.
IEEE Trans. Circuits Syst. II Express Briefs, 2004

High Input Voltage Step-Down DC-DC Converters for Integration in a Low Voltage CMOS Process.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Node Voltage Dependent Subthreshold Leakage Current Characteristics of Dynamic Circuits.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Forward body biased keeper for enhanced noise immunity in domino logic circuits.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Energy efficient dual threshold voltage dynamic circuits employing sleep switches to minimize subthreshold leakage.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Domino logic with variable threshold voltage keeper.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Dynamically Tuning Processor Resources with Adaptive Processing.
Computer, 2003

Monolithic DC-DC Converter Analysis And Mosfet Gate Voltage Optimization.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

2002
Managing static leakage energy in microprocessor functional units.
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

Low swing dual threshold voltage domino logic.
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002


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