Kil-Whan Lee

According to our database1, Kil-Whan Lee authored at least 8 papers between 2000 and 2007.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2007
A consistency-free memory architecture for sort-last parallel rendering processors.
J. Syst. Archit., 2007

Cooperative Cache System: A Low Power Cache System for Embedded Processors.
IEICE Trans. Electron., 2007

2006
A Processor Architecture with Effective Memory System for Sort-Last Parallel Rendering.
Proceedings of the Architecture of Computing Systems, 2006

2005
A pixel cache architecture with selective placement scheme based on z-test result.
Microprocess. Microsystems, 2005

2003
An Effective Pixel Rasterization Pipeline Architecture for 3D Rendering Processors.
IEEE Trans. Computers, 2003

2002
A Mid-Texturing Pixel Rasterization Pipeline Architecture for 3D Rendering Processors.
Proceedings of the 13th IEEE International Conference on Application-Specific Systems, 2002

2000
A Dual Data Cache System to Reflect the Principle of Locality Effectively.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

A Power Efficient Cache Structure for Embedded Processors Based on the Dual Cache Structure.
Proceedings of the Languages, 2000


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