Gi-Ho Park
Orcid: 0000-0001-7998-4302
According to our database1,
Gi-Ho Park
authored at least 47 papers
between 1996 and 2023.
Collaborative distances:
Collaborative distances:
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Bibliography
2023
CaMeL-Net: Centroid-aware metric learning for efficient multi-class cancer classification in pathology images.
Comput. Methods Programs Biomed., November, 2023
An Integrated Solution to Improve Performance of In-Memory Data Caching With an Efficient Item Retrieving Mechanism and a Near-Memory Accelerator.
IEEE Access, 2023
2022
A Low-power Programmable Machine Learning Hardware Accelerator Design for Intelligent Edge Devices.
ACM Trans. Design Autom. Electr. Syst., 2022
2018
IEICE Electron. Express, 2018
2017
NVM Way Allocation Scheme to Reduce NVM Writes for Hybrid Cache Architecture in Chip-Multiprocessors.
IEEE Trans. Parallel Distributed Syst., 2017
An analytical model based on performance demand of workload for energy-efficient heterogeneous multicore systems.
J. Parallel Distributed Comput., 2017
IEICE Electron. Express, 2017
Intelligence Boosting Engine (IBE): A hardware accelerator for processing sensor fusion and machine learning algorithm for a sensor hub SoC.
Proceedings of the 2017 IEEE Symposium in Low-Power and High-Speed Chips, 2017
2016
Cooperative cache memory (CCM) based on the performance efficiency for 3D stacked memory system.
IEICE Electron. Express, 2016
Comput. J., 2016
2015
IEEE Micro, 2015
Data Classification Management with its Interfacing Structure for Hybrid SLC/MLC PRAM Main Memory.
Comput. J., 2015
2014
IEICE Electron. Express, 2014
2013
An adaptive L2 cache prefetching mechanism for effective exploitation of abundant memory bandwidth of 3-D IC technology.
IEICE Electron. Express, 2013
Versatile stream buffer architecture to exploit the high memory bandwidth of 3-D IC technology.
IEICE Electron. Express, 2013
Phase detection based data prefetching for utilizing memory bandwidth of 3D integrated circuits.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013
2012
Performance and energy-efficiency analysis of hybrid cache memory based on SRAM-MRAM.
Proceedings of the International SoC Design Conference, 2012
2011
Adaptive prefetching scheme for exploiting massive memory bandwidth of 3-D IC technology.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011
2010
Design and implementation of Performance Analysis Unit (PAU) for AXI-based multi-core System on Chip (SOC).
Microprocess. Microsystems, 2010
An instruction-systolic programmable shader architecture for multi-threaded 3D graphics processing.
J. Parallel Distributed Comput., 2010
2009
A Way Enabling Mechanism Based on the Branch Prediction Information for Low Power Instruction Cache.
IEICE Trans. Electron., 2009
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
IEICE Electron. Express, 2009
IEICE Electron. Express, 2009
2008
2007
IEICE Trans. Electron., 2007
Proceedings of the 2007 ACM Symposium on Applied Computing (SAC), 2007
An efficient scheme for parallelizing fast search algorithm on SIMD architecture in H.264/AVC.
Proceedings of the ISCA 20th International Conference on Parallel and Distributed Computing Systems, 2007
2006
Microprocess. Microsystems, 2006
Microprocess. Microsystems, 2006
Proceedings of the High Performance Computing and Communications, 2006
Low-Power Data Cache Architecture by Address Range Reconfiguration for Multimedia Applications.
Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006
2005
PhD thesis, 2005
A new NAND-type flash memory package with smart buffer system for spatial and temporal localities.
J. Syst. Archit., 2005
2004
Power-Aware Deterministic Block Allocation for Low-Power Way-Selective Cache Structure.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004
2003
An Adaptive Multi-Module Cache with Hardware Prefetching Mechanism for Multimedia Applications.
Proceedings of the 11th Euromicro Workshop on Parallel, 2003
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
Appliaction-Specific Data Cache Systems.
Proceedings of the ISCA 18th International Conference Computers and Their Applications, 2003
2002
Proceedings of the 14th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2002), 2002
2000
A Dual Data Cache System to Reflect the Principle of Locality Effectively.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000
A Power Efficient Cache Structure for Embedded Processors Based on the Dual Cache Structure.
Proceedings of the Languages, 2000
1998
Methods to improve performance of instruction prefetching through balanced improvement of two primary performance factors.
J. Syst. Archit., 1998
1996
SIGARCH Comput. Archit. News, 1996