Hiroshi Nakamura

According to our database1, Hiroshi Nakamura authored at least 139 papers between 1984 and 2019.

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Bibliography

2019

2018

2017
Adaptive Power Management in Solar Energy Harvesting Sensor Node Using Reinforcement Learning.
ACM Trans. Embedded Comput. Syst., 2017

Scenario Analysis for Clean Energy Vehicles in UK Considering Introduction of Renewable Energy Sources.
IJAT, 2017

An Energy-Efficient Task Scheduling for Near-Realtime Systems with Execution Time Variation.
IEICE Transactions, 2017

Energy-aware task scheduling for near real-time periodic tasks on heterogeneous multicore processors.
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017

The Design and Implementation of Scalable Deep Neural Network Accelerator Cores.
Proceedings of the 11th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2017

Scalable deep neural network accelerator cores with cubic integration using through chip interface.
Proceedings of the International SoC Design Conference, 2017

Building block multi-chip systems using inductive coupling through chip interface.
Proceedings of the International SoC Design Conference, 2017

Dual notch-type high-order frinction-free force observers for force sensorless fine force control.
Proceedings of the IECON 2017 - 43rd Annual Conference of the IEEE Industrial Electronics Society, Beijing, China, October 29, 2017

Heart Rate and Heart Rate Variability Measuring System by Using Smartphone.
Proceedings of the 5th International Conference on Applied Computing and Information Technology, 2017

2016
An Operating System Guided Fine-Grained Power Gating Control Based on Runtime Characteristics of Applications.
IEICE Transactions, 2016

A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip.
IEICE Transactions, 2016

An adaptive energy-efficient task scheduling under execution time variation based on statistical analysis.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Normally-off power management for sensor nodes of global navigation satellite system.
Proceedings of the International SoC Design Conference, 2016

Fine force control without force sensor based on reaction force estimation system considering static friction and kinetic friction.
Proceedings of the IECON 2016, 2016

2015
A Fine-Grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional Units.
IEICE Transactions, 2015

Profile-based power shifting in interconnection networks with on/off links.
Proceedings of the International Conference for High Performance Computing, 2015

Position sensorless control with accelerometer for linear and curvilinear synchronous motor.
Proceedings of the IECON 2015, 2015

Runtime multi-optimizations for energy efficient on-chip interconnections1.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Immediate sleep: Reducing energy impact of peripheral circuits in STT-MRAM caches.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Energy-Efficient Continuous Task Scheduling for Near Real-Time Periodic Tasks.
Proceedings of the IEEE International Conference on Data Science and Data Intensive Systems, 2015

Suggestion-based interactive video digest design by user-system cooperative evolution.
Proceedings of the IEEE Congress on Evolutionary Computation, 2015

2014
Performance estimation of high performance computing systems with Energy Efficient Ethernet technology.
Computer Science - R&D, 2014

Area-Efficient Microarchitecture for Reinforcement of Turbo Mode.
IEICE Transactions, 2014

Video summarization support by Interactive Evolutionary Computation.
Proceedings of the 2014 Joint 7th International Conference on Soft Computing and Intelligent Systems (SCIS) and 15th International Symposium on Advanced Intelligent Systems (ISIS), 2014

Data-aware power management for periodic real-time systems with non-volatile memory.
Proceedings of the IEEE Non-Volatile Memory Systems and Applications Symposium, 2014

Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating.
Proceedings of the 2014 International Symposium on System-on-Chip, 2014

Proposal of position sensorless control and torque ripple compensation based on torque sensor feedback.
Proceedings of the IECON 2014 - 40th Annual Conference of the IEEE Industrial Electronics Society, Dallas, TX, USA, October 29, 2014

Design and evaluation of fine-grained power-gating for embedded microprocessors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Normally-off computing project: Challenges and opportunities.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Step climbing control of wheeled robot based on slip ratio taking account of work load shift by anti-dive force of suspensions and accerelation.
Proceedings of the IEEE 13th International Workshop on Advanced Motion Control, 2014

2013
A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface.
IEEE Micro, 2013

Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design.
IEICE Transactions, 2013

Imbalance of CPU temperatures in a blade system and its impact for power consumption of fans.
Cluster Computing, 2013

Performance modeling for designing NoC-based multiprocessors.
Proceedings of the 24th IEEE International Symposium on Rapid System Prototyping, 2013

Predict-More Router: A Low Latency NoC Router with More Route Predictions.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

Integrating Multi-GPU Execution in an OpenACC Compiler.
Proceedings of the 42nd International Conference on Parallel Processing, 2013

Power capping of CPU-GPU heterogeneous systems through coordinating DVFS and task mapping.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory.
Proceedings of the Design, Automation and Test in Europe, 2013

A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface.
Proceedings of the 2013 IEEE Symposium on Low-Power and High-Speed Chips, 2013

McRouter: Multicast within a router for high performance network-on-chips.
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013

2012
Geyser.
Proceedings of the Handbook of Energy-Aware and Green Computing - Two Volume Set., 2012

Evaluation of a New Power-Gating Scheme Utilizing Data Retentiveness on Caches.
IEICE Transactions, 2012

Efficient leakage power saving by sleep depth controlling for Multi-mode Power Gating.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Communication Library to Overlap Computation and Communication for OpenCL Application.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Stepwise sleep depth control for run-time leakage power saving.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

A novel power-gating scheme utilizing data retentiveness on caches.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

A multi-Vdd dynamic variable-pipeline on-chip router for CMPs.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Scalability-based manycore partitioning.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011
Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips.
IEEE Micro, 2011

Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units.
IPSJ Trans. System LSI Design Methodology, 2011

Sleep Transistor Sizing Method Using Accurate Delay Estimation Considering Input Vector Pattern and Non-linear Current Model.
IEICE Transactions, 2011

On-chip detection methodology for break-even time of power gated function units.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Cool Mega-Array: A highly energy efficient reconfigurable accelerator.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator.
Proceedings of the 2011 IEEE Symposium on Low-Power and High-Speed Chips, 2011

Geyser-2: The second prototype CPU with fine-grained run-time power gating.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Run-Time Power-Gating Techniques for Low-Power On-Chip Networks.
Proceedings of the Low Power Networks-on-Chip., 2011

2010
Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs.
Proceedings of the NOCS 2010, 2010

Adaptive power gating for function units in a microprocessor.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Power consumption and efficiency of cooling in a Data Center.
Proceedings of the 2010 11th IEEE/ACM International Conference on Grid Computing, 2010

Power Reduction Scheme of Fans in a Blade System by Considering the Imbalance of CPU Temperatures.
Proceedings of the 2010 IEEE/ACM Int'l Conference on Green Computing and Communications, 2010

Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Energy-Efficient Dynamic Instruction Scheduling Logic Through Instruction Grouping.
IEEE Trans. VLSI Syst., 2009

Pangea: An Eager Database Replication Middleware guaranteeing Snapshot Isolation without Modification of Database Servers.
PVLDB, 2009

Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Cooperative shared resource access control for low-power chip multiprocessors.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Power-performance modeling of heterogeneous cluster-based web servers.
Proceedings of the 2009 10th IEEE/ACM International Conference on Grid Computing, 2009

2008
Detecting Inconsistent Values Caused by Interaction Faults Using Automatically Located Implicit Redundancies.
Proceedings of the 14th IEEE Pacific Rim International Symposium on Dependable Computing, 2008

Discovering Implicit Redundancies in Network Communications for Detecting Inconsistent Values.
Proceedings of the Workshops Proceedings of the 8th IEEE International Conference on Data Mining (ICDM 2008), 2008

A fine-grain dynamic sleep control scheme in MIPS R3000.
Proceedings of the 26th International Conference on Computer Design, 2008

2007
Improving fairness, throughput and energy-efficiency on a chip multiprocessor through DVFS.
SIGARCH Computer Architecture News, 2007

A Proposal of New Dependable Database Middleware with Consistency and Concurrency Control.
Proceedings of the 13th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2007), 2007

A High Performance Cluster System Design by Adaptie Power Control.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Power reduction of chip multi-processors using shared resource control cooperating with DVFS.
Proceedings of the 25th International Conference on Computer Design, 2007

Fast Abstracts.
Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2007

Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

An intra-task dvfs technique based on statistical analysis of hardware events.
Proceedings of the 4th Conference on Computing Frontiers, 2007

2006
Noise Reduction from Genotyping Microarrays Using Probe Level Information.
In Silico Biology, 2006

Design Method of High Performance and Low Power Functional Units Considering Delay Variations.
IEICE Transactions, 2006

A System Assisting Acquisition of Japanese Expressions Through Read-Write-Hear-Speaking and Comparing Between Use Cases of Relevant Expressions.
Proceedings of the Knowledge-Based Intelligent Information and Engineering Systems, 2006

Energy-efficient dynamic instruction scheduling logic through instruction grouping.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

MegaProto/E: power-aware high-performance cluster with commodity technology.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

2005
Multidimensional support vector machines for visualization of gene expression data.
Bioinformatics, 2005

MegaProto: 1 TFlops/10kW Rack Is Feasible Even with Only Commodity Technology.
Proceedings of the ACM/IEEE SC2005 Conference on High Performance Networking and Computing, 2005

Dynamic Instruction Cascading on GALS Microprocessors.
Proceedings of the Integrated Circuit and System Design, 2005

Empirical Study for Optimization of Power-Performance with On-Chip Memory.
Proceedings of the High-Performance Computing - 6th International Symposium, 2005

MegaProto: A Low-Power and Compact Cluster for High-Performance Computing.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

A Small, Fast and Low-Power Register File by Bit-Partitioning.
Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005

Secret sequence comparison on public grid computing resources.
Proceedings of the 5th International Symposium on Cluster Computing and the Grid (CCGrid 2005), 2005

2004
Grid as a bioinformatic tool.
Parallel Computing, 2004

SCIMA-SMP: on-chip memory processor architecture for SMP.
Proceedings of the 3rd Workshop on Memory Performance Issues, 2004

Skewed Checkpointing for Tolerating Multi-Node Failures.
Proceedings of the 23rd International Symposium on Reliable Distributed Systems (SRDS 2004), 2004

Multidimensional support vector machines for visualization of gene expression data.
Proceedings of the 2004 ACM Symposium on Applied Computing (SAC), 2004

Dynamic Processor Throttling for Power Efficient Computations.
Proceedings of the Power-Aware Computer Systems, 4th International Workshop, 2004

Secret sequence comparison in distributed computing environments by interval sampling.
Proceedings of the 2004 IEEE Symposium on Computational Intelligence in Bioinformatics and Computational Biology, 2004

Data Movement Optimization for Software-Controlled On-Chip Memory.
Proceedings of the 8th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-8 2004), 2004

2003
A zero-time-overhead asynchronous four-phase controller.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Control signal sharing of asynchronous circuits using datapath delay information.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units.
Proceedings of the 2003 Design, 2003

A Method to Find Uniq e Sequences on Distrib ted Genomic Databases.
Proceedings of the 3rd IEEE International Symposium on Cluster Computing and the Grid (CCGrid 2003), 2003

Control Signal Sharing Using Data-Path Delay Information at Control Data Flow Graph Descriptions.
Proceedings of the 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 2003

Logic optimization for asynchronous speed independent controllers using transduction method.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Performance optimization of synchronous control units for datapaths with variable delay arithmetic units.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Software-controlled on-chip memory for high-performance and low-power computing.
SIGARCH Computer Architecture News, 2002

Formal Verification of a Pipelined Processor with New Memory.
Proceedings of the 9th Pacific Rim International Symposium on Dependable Computing (PRDC 2002), 2002

Rapid Analysis of Specificity of PCR Product on the Whole Genome.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2002

Logic Optimization for Asynchronous SI Controllers using Transduction Method.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Cache Line Impact on 3D PDE Solvers.
Proceedings of the High Performance Computing, 4th International Symposium, 2002

Design and evaluation of high performance microprocessor with reconfigurable on-chip memory.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001
The standard SpecC language.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Performance Evaluation of Cascade ALU Architecture for Asynchronous Super-Scalar Processors.
Proceedings of the 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 2001

2000
Real-time FEM Control System for Connected Piezoelectric Actuators.
JRM, 2000

Software Controlled Reconfigurable On-Chip Memory for High Performance Computing.
Proceedings of the Intelligent Memory Systems, Second International Workshop, 2000

SCIMA: Software Controlled Integrated Memory Architecture for High Performance Computing.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

1999
Augmenting Loop Tiling with Data Alignment for Improved Cache Performance.
IEEE Trans. Computers, 1999

CP-PACS: A massively parallel processor at the University of Tsukuba.
Parallel Computing, 1999

Performance of lattice QCD programs on CP-PACS.
Parallel Computing, 1999

1997
Improving cache Performance Through Tiling and Data Alignment.
Proceedings of the Solving Irregularly Structured Problems in Parallel, 1997

CP-PACS: A Massively Parallel Processor for Large Scale Scientific Calculations.
Proceedings of the 11th international conference on Supercomputing, 1997

A Data Alignment Technique for Improving Cache Performance.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Advanced processor design using hardware description language AIDL.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996
Adaptive routing technique on hypercrossbar network and its evaluation.
Systems and Computers in Japan, 1996

1994
Evaluation of Pseudo Vector Processor Based on Slide-Windowed Registers.
Proceedings of the 27th Annual Hawaii International Conference on System Sciences (HICSS-27), 1994

1993
A Scalar Architecture for Pseudo Vector Processing Based on Slide-Windowed Registers.
Proceedings of the 7th international conference on Supercomputing, 1993

1992
Pseudo Vector Processor Based on Register-Windowed Superscalar Pipeline.
Proceedings of the Proceedings Supercomputing '92, 1992

1990
Practical design assistance at register transfer level using a data path verifier.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

A Data Path Verifier for Register Transfer Level Using Temporal Logic Language Tokio.
Proceedings of the Computer-Aided Verification, 1990

1989
Logic Design Assistence Using Temporal Logic Based Language Tokio.
Proceedings of the Logic Programming '89, 1989

1987
Multilevel QAM Modulation Techniques for Digital Microwave Radios.
IEEE Journal on Selected Areas in Communications, 1987

1986
Theoretical Evalution of Signatures and CNR Penalties Caused by Modem Impairments in Multilevel QAM Digital Radio Modems.
IEEE Trans. Communications, 1986

1985
Using the Temporal Logic Programming Language Tokio for Algorithm Description and Automatic CMOS Gate Array Synthesis.
Proceedings of the Logic Programming '85, 1985

1984
A New 4 GHz 90 Mbps Digital Radio System Using 64-QAM Modulation.
Proceedings of the IEEE International Conference on Communications: Links for the Future, 1984


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