Kiyoshi Ishii

According to our database, Kiyoshi Ishii authored at least 15 papers between 1994 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

Analysis of propagation-delays in high-speed bipolar gates.

Yasushi Takahashi, Keisuke Eguchi, Akinobu Itoh, Kiyoshi Ishii

Proceedings of the 2015 International Symposium on Intelligent Signal Processing and Communication Systems, 2015

2012

Circuit technique for improving propagation delay times in CMOS source-coupled logic circuits.

Yuki Hagita, Kiyoshi Ishii

Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2012

2008

Estimation of Optimum Ion Energy for the Reduction of Resistivity in Bias Sputtering of ITO Thin Films.

Kiyoshi Ishii, Yoshifumi Saitou, Kengo Furutani, Hiroshi Sakuma, Yoshito Ikeda

IEICE Trans. Electron., 2008

Special Section on Functional Thin Films for Optical Applications.

Kiyoshi Ishii

IEICE Trans. Electron., 2008

2007

Adaptive partial median filter for early CT signs of acute cerebral infarction.

Yongbum Lee, Noriyuki Takahashi, Du-Yih Tsai, Kiyoshi Ishii

Int. J. Comput. Assist. Radiol. Surg., 2007

2005

High-bit-rate low-power decision circuit using InP-InGaAs HBT technology.

Kiyoshi Ishii, Hideyuki Nosaka, Kimikazu Sano, Koichi Murata, Minoru Ida, Kenji Kurishima, Michihiro Hirata, Tsugumichi Shibata, Takatomo Enoki

IEEE J. Solid State Circuits, 2005

2004

A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector.

Hideyuki Nosaka, Eiichi Sano, Kiyoshi Ishii, Minoru Ida, Kenji Kurishima, Shoji Yamahata, Tsugumichi Shibata, Hiroyuki Fukuyama, Mikio Yoneyama, Takatomo Enoki, Masahiro Muraguchi

IEEE J. Solid State Circuits, 2004

High-bit-rate low-power decision circuit using InP/InGaAs HBT technology [master-slave D-type flip-flop].

Kiyoshi Ishii, Hideyuki Nosaka, Minoru Ida, Kenji Kurishima, Michihiro Hirata, Takatorno Enoki, Tsugumichi Shibata

Proceedings of the 33rd European Solid-State Circuits Conference, 2004

2003

A 10-Gb/s data-pattern independent clock and data recovery circuit with a two-mode phase comparator.

Hideyuki Nosaka, Kiyoshi Ishii, Takatomo Enoki, Tsugumichi Shibata

IEEE J. Solid State Circuits, 2003

2002

Loop-parameter optimization of a PLL for a low-jitter 2.5-Gb/s one-chip optical receiver IC with 1: 8 DEMUX.

Keiji Kishine, Kiyoshi Ishii, Haruhiko Ichino

IEEE J. Solid State Circuits, 2002

Low-power 1: 16 DEMUX and one-chip CDR with 1: 4 DEMUX using InP-InGaAs heterojunction bipolar transistors.

Kiyoshi Ishii, Hideyuki Nosaka, Hiroki Nakajima, Kenji Kurishima, Minoru Ida, Noriyuki Watanabe, Yasurou Yamane, Eiichi Sano, Takatomo Enoki

IEEE J. Solid State Circuits, 2002

2000

A jitter suppression technique for a 2.48832 Gb/s clock and data recovery circuit.

Kiyoshi Ishii, Keiji Kishine, Haruhiko Ichino

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1995

Very-high-speed Si bipolar static frequency dividers with new T-type flip-flops.

Kiyoshi Ishii, Haruhiko Ichino, Minoru Togashi, Yoshiji Kobayashi, Chikara Yamaguchi

IEEE J. Solid State Circuits, January, 1995

1994

Maximum operating frequency in Si bipolar master-slave toggle flip-flop circuit.

Kiyoshi Ishii, Haruhiko Ichino, Chikara Yamaguchi

IEEE J. Solid State Circuits, July, 1994

High-bit-rate, high-input-sensitivity decision circuit using Si bipolar technology.

Kiyoshi Ishii, Haruhiko Ichino, Yoshiji Kobayashi, Chikara Yamaguchi

IEEE J. Solid State Circuits, May, 1994