Keiji Kishine

According to our database1, Keiji Kishine authored at least 58 papers between 1997 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 1988, "".

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Low-power and small-area 4-ch 25-Gb/s transimpedance amplifiers in 65-nm CMOS process.
IEICE Electron. Express, 2023

10Gb/s burst-mode driver circuit with on-chip bias switch for in-Vehicle optical networks.
IEICE Electron. Express, 2023

4-ch 25-Gb/s Small and Low-power VCSEL Driver Circuit with Unbalanced CML in 65-nm CMOS.
Proceedings of the 20th International SoC Design Conference, 2023

A 4×32-Gb/s VCSEL Driver with Adaptive Feedforward Equalization in 65-nm CMOS.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

High-Speed, Low-Power, and Small-Area Optical Receiver in 65-nm CMOS.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022
A Small-Area Integration of Optical Receiver Using Multi-Layer Inductors and Capacitor-Under-Pad.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

A 28-Gb/s VCSEL Driver with Variable Output Impedance in 65-nm CMOS.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

Smart Computational Resource Distribution System with Automatic Classification Interface for CPS.
Proceedings of the 19th International SoC Design Conference, 2022

Memory-Access Optimization for Acceleration and Power Saving of FPGA-Based Image Processing.
Proceedings of the 19th International SoC Design Conference, 2022

A Method for Implementing LSTM-Based Multiple-People Identification System for Non-Contact Health Monitoring on Small-Scale FPGA.
Proceedings of the 19th International SoC Design Conference, 2022

A Burst-Mode TIA with Automatic Power Saving and DC Wander Reduction in 65-nm CMOS.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

A Fine-Tuning Phase Shifter with Vector Synthesizer Using 65-nm CMOS for Beamforming in 24-GHz Band.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

Process Acceleration for HEVC Using Parallel Characteristics Calculation and Pixel Array Conversion.
Proceedings of the International Conference on Electronics, Information, and Communication, 2022

Capacitor Under Pad for Small Area Integration of High-Speed Signal-to-Differential Amplifier.
Proceedings of the International Conference on Electronics, Information, and Communication, 2022

A preamplifier circuit with offset-voltage control technique for 50-Gb/s CMOS PAM4 receiver.
Proceedings of the International Conference on Electronics, Information, and Communication, 2022

Method of Estimating Positions for Multiple People in Non-Contact Vital Signs Monitoring Systems.
Proceedings of the International Conference on Electronics, Information, and Communication, 2022

Supply-Variation-Tolerant Transimpedance Amplifier Using Non-Inverting Amplifier in 180-nm CMOS.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021
A Burst-Mode TIA with Adaptive Response and Stable Operation for in-Vehicle Optical Networks.
Proceedings of the 28th IEEE International Conference on Electronics, 2021

Implementation of Low-Energy LSTM with Parallel and Pipelined Algorithm in Small-Scale FPGA.
Proceedings of the International Conference on Electronics, Information, and Communication, 2021

5-Gb/s PAM4 Transmitter IC Using Compensation Circuit in an 180-nm CMOS.
Proceedings of the International Conference on Electronics, Information, and Communication, 2021

Supply Noise Reduction Filter for Parallel Integrated Transimpedance Amplifiers.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
Processing Time Reduction for JPEG Compression Using Pixel Array Conversion.
Proceedings of the International SoC Design Conference, 2020

2019
Impact of On-Chip Inductor and Power-Delivery-Network Stacking on Signal and Power Integrity.
IEICE Trans. Electron., 2019

Burst-Mode CMOS Transimpedance Amplifier Based on a Regulated-Cascode Circuit with Gain-Mode Switching.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019

Design of Crosstalk Noise Filter for Multi-Channel Transimpedance Amplifier.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

Optimization Technique of Memory Traffic for FPGA-Based Image Processing System.
Proceedings of the 2019 International SoC Design Conference, 2019

Frequency Discriminator Using a Simple AD Converter for Interface Systems.
Proceedings of the 2019 International SoC Design Conference, 2019

A wideband differential VCO based on double-short-path loop architecture.
Proceedings of the 2019 International SoC Design Conference, 2019

Suitable-Compensation Circuit Design for a PAM4 Transmitter in 180-nm CMOS.
Proceedings of the 2019 International SoC Design Conference, 2019

2018
A 25-Gb/s 13 mW clock and data recovery using C<sup>2</sup>MOS D-flip-flop in 65-nm CMOS.
Proceedings of the 2018 International Symposium on VLSI Design, 2018

Low-Power and High-Linearity Inductorless Low-Noise Amplifiers with Active-Shunt-Feedback in 65-nm CMOS Technology.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

A Wideband Differential VCO Based on Multiple-path Loop Architecture.
Proceedings of the International SoC Design Conference, 2018

A 25-Gb/s Low-Power Clock and Data Recovery with an Active-Stabilizing CML-CMOS Conversion.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017
FPGA-based transceiver circuit for labeling signal transmission system.
Proceedings of the International SoC Design Conference, 2017

Design method for inductorless low-noise amplifiers with active shunt-feedback in 65-nm CMOS.
Proceedings of the International SoC Design Conference, 2017

Compact implementation IIR filter in FPGA for noise reduction of sensor signal.
Proceedings of the International SoC Design Conference, 2017

25-Gb/s clock and data recovery IC using latch-load combined with CML buffer circuit for delay generation with 65-nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
Proposal for sensitive frequency demodulator for 10-Gb/s transmission labeling signal system.
Proceedings of the International SoC Design Conference, 2016

36-Gb/s CDR IC using simple passive loop filter combined with passive load in phase detector.
Proceedings of the International SoC Design Conference, 2016

Design of high-linearity delay detection circuit for 10-Gb/s communication system in 65-nm CMOS.
Proceedings of the International SoC Design Conference, 2016

2015
A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

2014
A 65-nm CMOS burst-mode CDR based on a GVCO with symmetric loops.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
Analysis and design based on small-signal equivalent circuit for a lO-GHz ring VCO with 65-nm CMOS.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

A 25-Gb/s LD driver with area-effective inductor in a 0.18-µm CMOS.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Area-Effective Inductive Peaking with Interwoven Inductor for High-Speed Laser-Diode Driver for Optical Communication System.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

Design method for an over-IO-Gb/s CMOS CML buffer circuit for delay control.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

A 16Gb/s area-efficient LD driver with interwoven inductor in a 0.18µm CMOS.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Bandwidth enhancement for high speed amplifier utilizing mutually coupled on-chip inductors.
Proceedings of the International SoC Design Conference, 2011

A 10.3Gbps translmpedance amplifier with mutually coupled inductors in 0.18-μm CMOS.
Proceedings of the International SoC Design Conference, 2011

2010
Throughput Estimation Method in Burst ACK Scheme for Optimizing Frame Size and Burst Frame Number Appropriate to SNR-Related Error Rate.
IEICE Trans. Commun., 2010

A 16Gbps laser-diode driver with interwoven peaking inductors in 0.18-µm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2007
MAC protocol based on cross-layer design methodology for fast link in wireless communication systems.
IEICE Electron. Express, 2007

2005
Physical Layer OAM&P Signaling Method for 10 Gbit/s Ethernet Transport over Optical Networks.
IEICE Trans. Commun., 2005

2004
PLL design technique by a loop-trajectory analysis taking decision-circuit phase margin into account for over-10-Gb/s clock and data recovery circuits.
IEEE J. Solid State Circuits, 2004

2002
Loop-parameter optimization of a PLL for a low-jitter 2.5-Gb/s one-chip optical receiver IC with 1: 8 DEMUX.
IEEE J. Solid State Circuits, 2002

2000
A jitter suppression technique for a 2.48832 Gb/s clock and data recovery circuit.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
A 2.5-Gb/s clock and data recovery IC with tunable jitter characteristics for use in LANs and WANs.
IEEE J. Solid State Circuits, 1999

1997
A high-speed, low-power bipolar digital circuit for Gb/s LSI's: current mirror control logic.
IEEE J. Solid State Circuits, 1997


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