Kohji Sakata

According to our database1, Kohji Sakata authored at least 5 papers between 2003 and 2006.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2006
Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond.
IEICE Trans. Electron., 2006

2005
An on-chip active decoupling circuit to suppress crosstalk in deep-submicron CMOS mixed-signal SoCs.
IEEE J. Solid State Circuits, 2005

Feedforward-type parasitic capacitance canceler and its application to 4 Gb/s T/H circuit.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
4-Gb/s track and hold circuit using parasitic capacitance canceller [flash ADC application].
Proceedings of the 33rd European Solid-State Circuits Conference, 2004

2003
Offset calibrating comparator array for 1.2-V, 6bit, 4-Gsample/s flash ADCs using 0.13μm generic CMOS technology.
Proceedings of the ESSCIRC 2003, 2003


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