Koichiro Ishibashi
Orcid: 0000-0001-6328-5371
According to our database1,
Koichiro Ishibashi
authored at least 65 papers
between 1994 and 2023.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2005, "For technical contributions to developments of low-power static random access memories.".
Timeline
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On csauthors.net:
Bibliography
2023
Proceedings of the IEEE International Conference on Consumer Electronics, 2023
2022
Systems on a Chip With 8 and 32 Bits Processors in 0.18-μm Technology for IoT Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Proceedings of the RIVF International Conference on Computing and Communication Technologies, 2022
Proceedings of the 2022 IEEE Sensors, Dallas, TX, USA, October 30 - Nov. 2, 2022, 2022
Deep Learning Approach for Classifying Bacteria types using Morphology of Bacterial Colony.
Proceedings of the 44th Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2022
2021
A Sub-μ W Reversed-Body-Bias 8-bit Processor on 65-nm Silicon-on-Thin-Box (SOTB) for IoT Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
High Accuracy Heartbeat Detection from CW-Doppler Radar Using Singular Value Decomposition and Matched Filter.
Sensors, 2021
Short time cardio-vascular pulses estimation for dengue fever screening via continuous-wave Doppler radar using empirical mode decomposition and continuous wavelet transform.
Biomed. Signal Process. Control., 2021
Proceedings of the 18th International SoC Design Conference, 2021
Proceedings of the 43rd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2021
2020
Contactless Heartbeat Detection from CW-Doppler Radar using Windowed-Singular Spectrum Analysis<sup>*</sup>.
Proceedings of the 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2020
2019
Dengue Fever Screening Using Vital Signs by Contactless Microwave Radar and Machine Learning.
Proceedings of the IEEE Sensors Applications Symposium, 2019
Proceedings of the IEEE International Conference on Industrial Cyber Physical Systems, 2019
Proceedings of the 41st Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2019
Precise Heart Rate Measurement Using Non-contact Doppler Radar Assisted by Machine-Learning-Based Sleep Posture Estimation.
Proceedings of the 41st Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2019
2018
83nJ/bit Transmitter Using Code-Modulated Synchronized-OOK on 65nm SOTB for Normally-Off Wireless Sensor Networks.
IEICE Trans. Electron., 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the 2018 IEEE SENSORS, New Delhi, India, October 28-31, 2018, 2018
Dengue Fever Detecting System Using Peak-detection of Data from Contactless Doppler Radar.
Proceedings of the 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2018
Energy-aware receiver-driven medium access control protocol for wireless energy-harvesting sensor networks.
Proceedings of the 15th IEEE Annual Consumer Communications & Networking Conference, 2018
Implementation of condition-aware receiver-initiated MAC protocol to realize energy-harvesting wireless sensor networks.
Proceedings of the 15th IEEE Annual Consumer Communications & Networking Conference, 2018
2017
Low-power enhanced temperature beat sensor with longer communication distance by data-recovery algorithm.
Proceedings of the 2017 IEEE SENSORS, Glasgow, United Kingdom, October 29, 2017
A 910nW delta sigma modulator using 65nm SOTB technology for mixed signal IC of IoT applications.
Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017
Non-contact acquisition of respiration and heart rates using Doppler radar with time domain peak-detection algorithm.
Proceedings of the 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2017
Short Time and Contactless Virus Infection Screening System with Discriminate Function Using Doppler Radar.
Proceedings of the Bio-inspired Computing: Theories and Applications, 2017
2016
Temperature beat: Persistent and energy harvesting wireless temperature sensing scheme.
Proceedings of the 2016 IEEE SENSORS, Orlando, FL, USA, October 30 - November 3, 2016, 2016
2015
A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode.
IEICE Trans. Electron., 2015
IEICE Electron. Express, 2015
Design of a low-power fixed-point 16-bit digital signal processor using 65nm SOTB process.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
2014
A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology.
Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014
2013
IEICE Trans. Electron., 2013
2012
On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction.
IEICE Trans. Electron., 2012
An on-chip 250 mA 40 nm CMOS digital LDO using dynamic sampling clock frequency scaling with offset-free TDC-based voltage sensor.
Proceedings of the IEEE 25th International SOC Conference, 2012
2011
On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch.
IEICE Trans. Electron., 2011
On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blocks with tri-mode power gating structure.
Proceedings of the 37th European Solid-State Circuits Conference, 2011
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
A 1.39-V input fast-transient-response digital LDO composed of low-voltage MOS transistors in 40-nm CMOS process.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
2010
A Low-Power Wide-Range Clock Synchronizer With Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS.
IEEE J. Solid State Circuits, 2010
2008
A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die.
IEEE J. Solid State Circuits, 2008
2007
A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits.
IEEE J. Solid State Circuits, 2007
Substrate-Noise and Random-Variability Reduction with Self-Adjusted Forward Body Bias.
IEICE Trans. Electron., 2007
A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2006
Soft Error Hardened Latch Scheme with Forward Body Bias in a 90-nm Technology and Beyond.
IEICE Trans. Electron., 2006
Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond.
IEICE Trans. Electron., 2006
2005
Frequency-voltage cooperative CPU power control: A design rule and its application by feedback prediction.
Syst. Comput. Jpn., 2005
An on-chip active decoupling circuit to suppress crosstalk in deep-submicron CMOS mixed-signal SoCs.
IEEE J. Solid State Circuits, 2005
IEICE Electron. Express, 2005
Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
Substrate-noise and random-fluctuations reduction with self-adjusted forward body bias.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
2004
0.4-V logic-library-friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme.
IEEE J. Solid State Circuits, 2004
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004
2003
16.7-fA/cell tunnel-leakage-suppressed 16-Mb SRAM for handling cosmic-ray-induced multierrors.
IEEE J. Solid State Circuits, 2003
Offset calibrating comparator array for 1.2-V, 6bit, 4-Gsample/s flash ADCs using 0.13μm generic CMOS technology.
Proceedings of the ESSCIRC 2003, 2003
2002
A system LSI memory redundancy technique using an ie-flash (inverse-gate-electrode flash) programming circuit.
IEEE J. Solid State Circuits, 2002
A 1.2-GIPS/W microprocessor using speed-adaptive threshold-voltage CMOS with forward bias.
IEEE J. Solid State Circuits, 2002
2001
Universal-V<sub>dd</sub> 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell.
IEEE J. Solid State Circuits, 2001
CMOS process compatible ie-Flash (inverse gate electrode Flash) technology for system-on-a-chip.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001
1999
A separated bit-line unified cache: Conciliating small on-chip cache die-area and low miss ratio.
IEEE Trans. Very Large Scale Integr. Syst., 1999
An 18-μA standby current 1.8-V, 200-MHz microprocessor with self-substrate-biased data-retention mode.
IEEE J. Solid State Circuits, 1999
1998
A delay distribution squeezing scheme with speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) for low voltage LSIs.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998
1996
A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators.
IEEE J. Solid State Circuits, 1996
1995
IEEE J. Solid State Circuits, November, 1995
IEEE J. Solid State Circuits, April, 1995
1994
IEEE J. Solid State Circuits, April, 1994