Yoshihide Komatsu

According to our database1, Yoshihide Komatsu authored at least 11 papers between 2004 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
A 0.6-V Adaptive Voltage Swing Serial Link Transmitter Using Near Threshold Body Bias Control and Jitter Estimation.
IEICE Trans. Electron., 2020

2019
A 0.25-27-Gb/s PAM4/NRZ Transceiver With Adaptive Power CDR and Jitter Analysis.
IEEE J. Solid State Circuits, 2019

2018
A 0.25-27Gb/s Wideband PAM4/NRZ Transceiver with Adaptive Power CDR for 8K System.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2011
An Ultra-Wide Range Bi-Directional Transceiver With Adaptive Power Control Using Background Replica VCO Gain Calibration.
IEEE J. Solid State Circuits, 2011

2009
A 125-1250 MHz Process-Independent Adaptive Bandwidth Spread Spectrum Clock Generator With Digital Controlled Self-Calibration.
IEEE J. Solid State Circuits, 2009

2008
Transceiver Macro with Spread-Spectrum Clocking Capability for AC-Coupled Cable Interfaces.
IEICE Trans. Electron., 2008

2007
Substrate-Noise and Random-Variability Reduction with Self-Adjusted Forward Body Bias.
IEICE Trans. Electron., 2007

2006
Soft Error Hardened Latch Scheme with Forward Body Bias in a 90-nm Technology and Beyond.
IEICE Trans. Electron., 2006

Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond.
IEICE Trans. Electron., 2006

2005
Substrate-noise and random-fluctuations reduction with self-adjusted forward body bias.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
A soft-error hardened latch scheme for SoC in a 90 nm technology and beyond.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004


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