Koichi Takasugi

According to our database1, Koichi Takasugi authored at least 13 papers between 1995 and 2024.

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Bibliography

2024
Fast WDM provisioning with minimal probing: the first field experiments for DC exchanges.
J. Opt. Commun. Netw., February, 2024

Semi-Automatic Line-System Provisioning with Integrated Physical-Parameter-Aware Methodology: Field Verification and Operational Feasibility.
CoRR, 2024

2023
Ultra-Low-Latency 8K-Video-Transmission System Utilizing Whitebox Transponder with Disaggregation Configuration.
IEICE Trans. Electron., June, 2023

Dynamic Optical Path Provisioning for Alien Access Links: Architecture, Demonstration, and Challenges.
IEEE Commun. Mag., April, 2023

Uncompressed 8K-video-transmission System for Remote Production Secured by Post-quantum Cryptography.
Proceedings of the IEEE International Symposium on Broadband Multimedia Systems and Broadcasting, 2023

2022
Two-step wireless link quality prediction using multi-camera images.
Proceedings of the 2022 IEEE 33rd Annual International Symposium on Personal, 2022

Ultra-low Latency 8K Video-transmission System Utilizing Disaggregation Configuration.
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2022

2021
Remote Production System Concept Utilizing Optical Networks and Proof-of-concept for 8K Production.
Proceedings of the IEEE International Symposium on Broadband Multimedia Systems and Broadcasting, 2021

2013
Leveraging real-world data while protecting privacy Framework using personal agent system for distributed data.
Proceedings of the 10th IEEE Consumer Communications and Networking Conference, 2013

2007
Recent Developments in Wide Area Ubiquitous Network Research.
Proceedings of the International Symposium on Autonomous Decentralized Systems (ISADS 2007), 2007

2003
Seamless Service Platform for Following a User?s Movement in a Dynamic Network Environment.
Proceedings of the First IEEE International Conference on Pervasive Computing and Communications (PerCom'03), 2003

1995
A 2.6-ns wave-pipelined CMOS SRAM with dual-sensing-latch circuits.
IEEE J. Solid State Circuits, April, 1995

A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers.
IEEE J. Solid State Circuits, April, 1995


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