Toshiaki Yamanaka

According to our database, Toshiaki Yamanaka authored at least 16 papers between 1989 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

TSP integrality gap via 2-edge-connected multisubgraph problem under coincident IP optima.

Toshiaki Yamanaka

CoRR, November, 2025

2013

Accuracy assessment of kinect body tracker in instant posturography for balance disorders.

Hiroyuki Funaya, Tomohiro Shibata, Yoshiro Wada, Toshiaki Yamanaka

Proceedings of the 7th International Symposium on Medical Information and Communication Technology, 2013

1995

A 300-MHz 4-Mb wave-pipeline CMOS SRAM using a multiphase PLL.

Koichiro Ishibashi, Kunihiro Komiyaji, Hiroshi Toyoshima, Masataka Minami, Nagatoshi Ohki, Hiroshi Ishida, Toshiaki Yamanaka, Takahiro Nagano, Takashi Nishida

IEEE J. Solid State Circuits, November, 1995

A 2.6-ns wave-pipelined CMOS SRAM with dual-sensing-latch circuits.

Suguru Tachibana, Hisayuki Higuchi, Koichi Takasugi, Katsuro Sasaki, Toshiaki Yamanaka, Yoshinobu Nakagome

IEEE J. Solid State Circuits, April, 1995

A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers.

Koichiro Ishibashi, Koichi Takasugi, Kunihiro Komiyaji, Hiroshi Toyoshima, Toshiaki Yamanaka, Akira Fukami, Naotaka Hashimoto, Nagatoshi Ohki, Akihiro Shimizu, Takashi Hashimoto, Takahiro Nagano, Takashi Nishida

IEEE J. Solid State Circuits, April, 1995

A 4.4 ns CMOS 54⨉54-b multiplier using pass-transistor multiplexer.

Norio Ohkubo, Makoto Suzuki, Toshinobu Shinbo, Toshiaki Yamanaka, Akihiro Shimizu, Katsuro Sasaki, Yoshinobu Nakagome

IEEE J. Solid State Circuits, March, 1995

1994

A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiers.

Koichiro Ishibashi, Kunihiro Komiyaji, Sadayuki Morita, Toshiro Aoto, Shuji Ikeda, Kyoichiro Asayama, Atsuyosi Koike, Toshiaki Yamanaka, Naotaka Hashimoto, Haruhito Iida, Fumio Kojima, Koichi Motohashi, Katsuro Sasaki

IEEE J. Solid State Circuits, April, 1994

1993

A 1.5-ns 32-b CMOS ALU in double pass-transistor logic.

Makoto Suzuki, Norio Ohkubo, Toshinobu Shinbo, Toshiaki Yamanaka, Akihiro Shimizu, Katsuro Sasaki, Yoshinobu Nakagome

IEEE J. Solid State Circuits, November, 1993

A 16-Mb CMOS SRAM with a 2.3- mu m² single-bit-line memory cell.

Katsuro Sasaki, Kiyotsugu Ueda, Koichi Takasugi, Hiroshi Toyoshima, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Nagatoshi Ohki

IEEE J. Solid State Circuits, November, 1993

1992

A 7-ns 140-mW 1-Mb CMOS SRAM with current sense amplifier.

Katsuro Sasaki, Koichiro Ishibashi, Kiyotsugu Ueda, Kunihiro Komiyaji, Toshiaki Yamanaka, Naotaka Hashimoto, Hiroshi Toyoshima, Fumio Kojima, Akihiro Shimizu

IEEE J. Solid State Circuits, November, 1992

A 1-V TFT-load SRAM using a two-step word-voltage method.

Koichiro Ishibashi, Koichi Takasugi, Toshiaki Yamanaka, Takashi Hashimoto, Katsuro Sasaki

IEEE J. Solid State Circuits, November, 1992

A 1.7-V adjustable I/O interface for low-voltage fast SRAMs.

Koichiro Ishibashi, Katsuro Sasaki, Toshiaki Yamanaka, Hiroshi Toyoshima, Fumio Kojima

IEEE J. Solid State Circuits, April, 1992

1990

A 23-ns 4-Mb CMOS SRAM with 0.2- mu A standby current.

Katsuro Sasaki, Koichiro Ishibashi, Katsuhiro Shimohigashi, Toshiaki Yamanaka, Nobuyuki Moriwake, Shigeru Honjo, Shuji Ikeda, Atsuyoshi Koike, Satoshi Meguro, Osamu Minato

IEEE J. Solid State Circuits, October, 1990

A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logic.

Kazuo Yano, Toshiaki Yamanaka, Takashi Nishida, Masayoshi Saito, Katsuhiro Shimohigashi, Akihiro Shimizu

IEEE J. Solid State Circuits, April, 1990

An alpha -immune, 2-V supply voltage SRAM using a polysilicon PMOS load cell.

Koichiro Ishibashi, Toshiaki Yamanaka, Katsuhiro Shimohigashi

IEEE J. Solid State Circuits, February, 1990

1989

A 9-ns 1-Mbit CMOS SRAM.

Katsuro Sasaki, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Takashi Nishida, Katsuhiro Shimohigashi, Shoji Hanamura, Shigeru Honjo

IEEE J. Solid State Circuits, October, 1989