Konstantinos Manolopoulos

According to our database, Konstantinos Manolopoulos authored at least 10 papers between 2006 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2017

A novel FPGA-based track reconstruction approach for the level-1 trigger of the CMS experiment at CERN.

Robin Aggleton, Luis E. Ardila-Perez, Fionn Amhairghen Ball, Matthias Norbert Balzer, James John Brooke, Luigi Calligaris, Michele Caselle, Davide Cieri, Emyr John Clement, Geoffrey Hall, Kristian Harder, Peter R. Hobson, Gregory M. Iles, Thomas James, Konstantinos Manolopoulos, Takashi Matsushita, Alexander D. Morton, David Newbold, Sudarshan Paramesvaran, Mark Franco Pesaresi, Ivan D. Reid, Andrew W. Rose, Oliver Sander, Thomas Schuh, Claire Shepherd-Themistocleous, Antoni Shtipliyski, Sioni Paris Summers, Alexander D. Tapper, Ian Tomalin, Kirika Uchida, Paschalis Vichoudis, Marc Weber

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2016

An efficient multiple precision floating-point Multiply-Add Fused unit.

Konstantinos Manolopoulos, Dionisios I. Reisis, Vassilios A. Chouliaras

Microelectron. J., 2016

2012

Signal processing for deep-sea observatories with reconfigurable hardware.

Konstantinos Manolopoulos, A. Belias, Georgios Georgis, Dionysios I. Reisis, E. G. Anasontzis

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011

An efficient multiple precision floating-point multiplier.

Konstantinos Manolopoulos, Dionisios I. Reisis, Vassilios A. Chouliaras

Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

2010

Fully Systolic FFT Architecture for Giga-sample Applications.

Konstantinos Babionitakis, Vassilios A. Chouliaras, Konstantinos Manolopoulos, Konstantinos Nakos, Dionysios I. Reisis, Nikolaos Vlassopoulos

J. Signal Process. Syst., 2010

An efficient dual-mode floating-point Multiply-Add Fused Unit.

Konstantinos Manolopoulos, Dionysios I. Reisis, Vassilios A. Chouliaras

Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009

A configurable length, Fused Multiply-Add floating point unit for a VLIW processor.

Vassilios A. Chouliaras, Konstantinos Manolopoulos, Dionysios I. Reisis

Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

2008

Customization of an embedded RISC CPU with SIMD extensions for video encoding: A case study.

Vassilios A. Chouliaras, Vincent M. Dwyer, Shahrukh Agha, José L. Núñez-Yáñez, Dionysios I. Reisis, Konstantinos Nakos, Konstantinos Manolopoulos

Integr., 2008

2007

High Performance 16K, 64K, 256K complex points VLSI Systolic FFT Architectures.

Konstantinos Manolopoulos, Konstantinos Nakos, Dionysios I. Reisis, Nikolaos Vlassopoulos, Vassilios A. Chouliaras

Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006

A High Performance VLSI FFT Architecture.

Konstantinos Babionitakis, Konstantinos Manolopoulos, Konstantinos Nakos, Dionysios I. Reisis, Nikolaos Vlassopoulos, Vassilios A. Chouliaras

Proceedings of the 13th IEEE International Conference on Electronics, 2006