José L. Núñez-Yáñez

According to our database1, José L. Núñez-Yáñez authored at least 104 papers between 2001 and 2020.

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Bibliography

2020
Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA platform.
J. Supercomput., 2020

A Streaming Dataflow Engine for Sparse Matrix-Vector Multiplication Using High-Level Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Intra and inter-core power modelling for single-ISA heterogeneous processors.
Int. J. Embed. Syst., 2020

Evaluation of hybrid run-time power models for the ARM big.LITTLE architecture.
CoRR, 2020

High-Performance Simultaneous Multiprocessing for Heterogeneous System-on-Chip.
CoRR, 2020

Performance and Energy Trade-Offs for Parallel Applications on Heterogeneous Multi-Processing Systems.
CoRR, 2020

Remaining Useful Life Estimation Using Long Short-Term Memory Neural Networks and Deep Fusion.
IEEE Access, 2020

Run-Time Power Modelling in Embedded GPUs with Dynamic Voltage and Frequency Scaling.
Proceedings of the PARMA-DITAM@HiPEAC 2020: 11th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures / 9th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2020

Sparse Matrix-Dense Matrix Multiplication on Heterogeneous CPU+FPGA Embedded System.
Proceedings of the PARMA-DITAM@HiPEAC 2020: 11th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures / 9th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2020

2019
Correction to: Simultaneous multiprocessing in a software-defined heterogeneous FPGA.
J. Supercomput., 2019

Simultaneous multiprocessing in a software-defined heterogeneous FPGA.
J. Supercomput., 2019

Energy Proportional Neural Network Inference with Adaptive Voltage and Frequency Scaling.
IEEE Trans. Computers, 2019

Exploring heterogeneous scheduling for edge computing with CPU and FPGA MPSoCs.
J. Syst. Archit., 2019

Relationship Detection Measures for Binary SoC Data.
CoRR, 2019

High-Performance Ultrasonic Levitation with FPGA-based Phased Arrays.
CoRR, 2019

Heterogeneous FPGA+GPU Embedded Systems: Challenges and Opportunities.
CoRR, 2019

Performance and Energy Efficiency Trade-Offs in Single-ISA Heterogeneous Multi-Processing for Parallel Applications.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Visualizations for Understanding SoC Behaviour.
Proceedings of the 15th Conference on Ph.D. Research in Microelectronics and Electronics, 2019

Relationship Estimation Metrics for Binary SoC Data.
Proceedings of the Machine Learning, Optimization, and Data Science, 2019

Energy Proportional Heterogenous Computing with Reconfigurable MPSoC.
Proceedings of the 17th International Conference on High Performance Computing & Simulation, 2019

Ultrasonic Levitation with Software-Defined FPGAs and Electronically Phased Arrays.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2019

2018
Dynamic Energy Management of FPGA Accelerators in Embedded Systems.
ACM Trans. Embed. Comput. Syst., 2018

Reconfigurable Network Stream Processing on Virtualized FPGA Resources.
Int. J. Reconfigurable Comput., 2018

Parallelizing Workload Execution in Embedded and High-Performance Heterogeneous Systems.
CoRR, 2018

Workload Partitioning Strategy for Improved Parallelism on FPGA-CPU Heterogeneous Chips.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

Multi-precision convolutional neural networks on heterogeneous hardware.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Energy proportional streaming spiking neural network in a reconfigurable system.
Microprocess. Microsystems, 2017

Adaptive voltage scaling in a heterogeneous FPGA device with memory and logic in-situ detectors.
Microprocess. Microsystems, 2017

Synchronizing reconfiguration of coherent functions on disaggregated FPGA resources.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

Simultaneous Multiprocessing on a FPGA+CPU Heterogeneous System-On-Chip.
Proceedings of the Parallel Computing is Everywhere, 2017

Pipelined Streaming Computation of Histogram in FPGA OpenCL.
Proceedings of the Parallel Computing is Everywhere, 2017

A systematic approach to design and optimise streaming applications on FPGA using high-level synthesis.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Optimal compression of vibration data with lifting wavelet transform and context-based arithmetic coding.
Proceedings of the 25th European Signal Processing Conference, 2017

2016
Energy Optimization in Commercial FPGAs with Voltage, Frequency and Logic Scaling.
IEEE Trans. Computers, 2016

Editorial to special issue on energy efficient architectures for embedded systems.
EURASIP J. Embed. Syst., 2016

Energy Efficient Video Fusion with Heterogeneous CPU-FPGA Devices.
CoRR, 2016

CPCIe: A compression-enabled PCIe core for energy and performance optimization.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016

Energy proportional computing with OpenCL on a FPGA-based overlay architecture.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016

Energy efficient video fusion with heterogeneous CPU-FPGA devices.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Computing to the Limit with Heterogeneous CPU-FPGA Devices in a Video Fusion Application.
Proceedings of the Applied Reconfigurable Computing - 12th International Symposium, 2016

2015
Adaptive Voltage Scaling with In-Situ Detectors in Commercial FPGAs.
IEEE Trans. Computers, 2015

Biologically compatible neural networks with reconfigurable hardware.
Microprocess. Microsystems, 2015

Guest Editorial.
IET Comput. Digit. Tech., 2015

Workload distribution and balancing in FPGAs and CPUs with OpenCL and TBB.
Proceedings of the Parallel Computing: On the Road to Exascale, 2015

Optimised OpenCL workgroup synthesis for hybrid ARM-FPGA devices.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Energy optimization of FPGA-based stream-oriented computing with power gating.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Evaluation of Hybrid Run-Time Power Models for the ARM Big.LITTLE Architecture.
Proceedings of the 13th IEEE International Conference on Embedded and Ubiquitous Computing, 2015

2014
Bayesian Video Super-Resolution With Heavy-Tailed Prior Models.
IEEE Trans. Circuits Syst. Video Technol., 2014

Energy efficient Reconfigurable Computing with Adaptive Voltage and Logic scaling.
SIGARCH Comput. Archit. News, 2014

Run-time power and performance scaling in 28 nm FPGAs.
IET Comput. Digit. Tech., 2014

eXtended Torus routing algorithm for networks-on-chip: a routing algorithm for dynamically reconfigurable networks-on-chip.
IET Comput. Digit. Tech., 2014

Neuron Dynamics of Two-compartment Traub Model for Hardware-based Emulation.
Proceedings of the NCTA 2014 - Proceedings of the International Conference on Neural Computation Theory and Applications, part of IJCCI 2014, Rome, Italy, 22, 2014

Joint video fusion and super resolution based on Markov random fields.
Proceedings of the 2014 IEEE International Conference on Image Processing, 2014

Power modelling and capping for heterogeneous ARM/FPGA SoCs.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Run-time power gating in hybrid ARM-FPGA devices.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Accurate power control and monitoring in ZYNQ boards.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Run-time power and performance scaling with CPU-FPGA hybrids.
Proceedings of the 2014 NASA/ESA Conference on Adaptive Hardware and Systems, 2014

2013
Biophysically Accurate Foating Point Neuroprocessors for Reconfigurable Logic.
IEEE Trans. Computers, 2013

Enabling accurate modeling of power and energy consumption in an ARM-based System-on-Chip.
Microprocess. Microsystems, 2013

Numerically efficient and biophysically accurate neuroprocessing platform.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

Video super-resolution using low rank matrix completion.
Proceedings of the IEEE International Conference on Image Processing, 2013

2012
Cogeneration of Fast Motion Estimation Processors and Algorithms for Advanced Video Coding.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Adaptive Voltage Scaling in a Dynamically Reconfigurable FPGA-Based Platform.
ACM Trans. Reconfigurable Technol. Syst., 2012

Video Super-Resolution Using Generalized Gaussian Markov Random Fields.
IEEE Signal Process. Lett., 2012

Lossless video compression based on backward adaptive pixel-based fast motion estimation.
Signal Process. Image Commun., 2012

Fast and low overhead architectural transaction level modelling for large-scale network-on-chip simulation.
IET Comput. Digit. Tech., 2012

Run-time stochastic task mapping on a large scale network-on-chip with dynamically reconfigurable tiles.
IET Comput. Digit. Tech., 2012

Exploring dynamically reconfigurable multicore designs with NoRC designer.
Proceedings of the 2012 International Conference on High Performance Computing & Simulation, 2012

Approximate alpha-stable Markov Random Fields for video super-resolution.
Proceedings of the 20th European Signal Processing Conference, 2012

2011
Multi-standard reconfigurable motion estimation processor for hybrid video codecs.
IET Comput. Digit. Tech., 2011

2010
Task Dispersal Measurement in Dynamic Reconfigurable NoCs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Effective modelling of large NoCs using SystemC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Dynamic Reconfiguration Optimisation with Streaming Data Decompression.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

SystemC Architectural Transaction Level Modelling for Large NoCs.
Proceedings of the 2010 Forum on specification & Design Languages, 2010

2009
Backward Adaptive Pixel-based Fast Predictive Motion Estimation.
IEEE Signal Process. Lett., 2009

Adaptive stochastic routing in fault-tolerant on-chip networks.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

A biophysically accurate floating point somatic neuroprocessor.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

A toolset for the analysis and optimization of motion estimation algorithms and processors.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Run-time resource management in fault-tolerant network on reconfigurable chips.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Energy optimization in a Network-on-Chip with dynamically reconfigurable processing nodes.
Proceedings of the IEEE International Conference on Control Applications, 2009

2008
A Novel Delta Sigma Control System Processor and Its VLSI Implementation.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Customization of an embedded RISC CPU with SIMD extensions for video encoding: A case study.
Integr., 2008

Adaptive routing strategies for fault-tolerant on-chip networks in dynamically reconfigurable systems.
IET Comput. Digit. Tech., 2008

Evaluating dynamic partial reconfiguration in the integer pipeline of a FPGA-based opensource processor.
Proceedings of the FPL 2008, 2008

A configurable and programmable motion estimation processor for the H.264 video codec.
Proceedings of the FPL 2008, 2008

Power/Area Analysis of a FPGA-Based Open-Source Processor using Partial Dynamic Reconfiguration.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Fault-tolerant dynamically reconfigurable NoC-based SoC.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

Lossless Compression for Space Imagery in a Dynamically Reconfigurable Architecture.
Proceedings of the Reconfigurable Computing: Architectures, 2008

Statistical Lossless Compression of Space Imagery and General Data in a Reconfigurable Architecture.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2008

2007
Hardware architecture for lossless image compression based on context-based modeling and arithmetic coding.
Proceedings of the 2007 IEEE International SOC Conference, 2007

On the Hardware Reduction of z-Datapath of Vectoring CORDIC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Dynamic Voltage Scaling in a FPGA-based System-on-Chip.
Proceedings of the FPL 2007, 2007

2006
Hardware assisted rate distortion optimization with embedded CABAC accelerator for the H.264 advanced video codec.
IEEE Trans. Consumer Electron., 2006

A Novel Processor Architecture for Real-Time Control.
Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006

2005
High-performance arithmetic coding VLSI macro for the H264 video compression standard.
IEEE Trans. Consumer Electron., 2005

A multi-standard video accelerator based on a vector architecture.
IEEE Trans. Consumer Electron., 2005

A Configurable Statistical Lossless Compression Core Based on Variable Order Markov Modeling and Arithmetic Coding.
IEEE Trans. Computers, 2005

Applying data-parallel and scalar optimizations for the efficient implementation of the G.729A and G.723.1 speech coding standards.
Proceedings of the Signal and Image Processing (SIP 2005), 2005

Configurable Multiprocessors for High-Performance MPEG-4 Video Coding.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Design and Implementation of a High-Performance and Silicon Efficient Arithmetic Coding Accelerator for the H.264 Advanced Video Codec.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

A Thread and Data-Parallel MPEG-4 Video Encoder for a System-On-Chip Multiprocessor.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2003
Scalar coprocessors for accelerating the G723.1 and G729A speech coders.
IEEE Trans. Consumer Electron., 2003

A code compression scheme for improving SoC performance.
Proceedings of the 2003 International Symposium on System-on-Chip, 2003

2001
Gbit/second lossless data compression hardware.
PhD thesis, 2001


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