Vassilios A. Chouliaras

According to our database, Vassilios A. Chouliaras authored at least 48 papers between 2003 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

Development of Sensorised Resistance Band for Objective Exercise Measurement: Activities Classification Trial.

Jianjia Ma, Eef Hogervorst, Daniele Magistro, Vassilios A. Chouliaras, Massimiliano Zecca

Proceedings of the 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2018

2017

Shape reconstruction using instruction systolic array.

Partheepan Kandaswamy, James A. Flint, Vassilios A. Chouliaras

Proceedings of the 2017 IEEE SENSORS, Glasgow, United Kingdom, October 29, 2017

2016

An efficient multiple precision floating-point Multiply-Add Fused unit.

Konstantinos Manolopoulos, Dionisios I. Reisis, Vassilios A. Chouliaras

Microelectron. J., 2016

VThreads: A novel VLIW chip multiprocessor with hardware-assisted PThreads.

Vassilios A. Chouliaras, David Stevens, Vincent M. Dwyer

Microprocess. Microsystems, 2016

An OpenCL software compilation framework targeting an SoC-FPGA VLIW chip multiprocessor.

Samuel J. Parker, Vassilios A. Chouliaras

J. Syst. Archit., 2016

2013

Bidirectional electromigration failure.

M. K. Lim, Vassilios A. Chouliaras, Chee Lip Gan, Vincent M. Dwyer

Microelectron. Reliab., 2013

Architecture, performance modeling and VLSI implementation methodologies for ASIC vector processors: A case study in telephony workloads.

Vassilios A. Chouliaras, Konstantia Koutsomyti, Simon Parr, David J. Mulvaney, Mark Milward

Microprocess. Microsystems, 2013

Autonomous learning design in system-on-chip.

Yimin Zhou, Ludovic A. Krundel, David J. Mulvaney, Vassilios A. Chouliaras, Guoqing Xu, Guoqiang Fu

Proceedings of the IEEE International Conference on Robotics and Biomimetics, 2013

2012

BioThreads: A Novel VLIW-Based Chip Multiprocessor for Accelerating Biomedical Image Processing Applications.

David Stevens, Vassilios A. Chouliaras, Vicente Azorin-Peris, Jia Zheng, Angelos Echiadis, Sijung Hu

IEEE Trans. Biomed. Circuits Syst., 2012

Embedded UML design flow to the configurable LE1 MultiCore VLIW processor.

Mark Milward, David Stevens, Vassilios A. Chouliaras

Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

2011

An efficient multiple precision floating-point multiplier.

Konstantinos Manolopoulos, Dionisios I. Reisis, Vassilios A. Chouliaras

Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

Customizing a VLIW Chip Multiprocessor for Motion Estimation Algorithms.

Vassilios A. Chouliaras, George Lentaris, Dionisios I. Reisis, David Stevens

Proceedings of the ARCS 2011, 2011

2010

Fully Systolic FFT Architecture for Giga-sample Applications.

Konstantinos Babionitakis, Vassilios A. Chouliaras, Konstantinos Manolopoulos, Konstantinos Nakos, Dionysios I. Reisis, Nikolaos Vlassopoulos

J. Signal Process. Syst., 2010

LE1: A Parameterizable VLIW Chip-Multiprocessor with Hardware PThreads Support.

David Stevens, Vassilios A. Chouliaras

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Autonomous Design in VLSI: Growing and Learning on Silicon.

Ludovic A. Krundel, David J. Mulvaney, Vassilios A. Chouliaras

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Autonomous Design in VLSI: An In-House Universal Cellular Neural Platform.

Ludovic A. Krundel, David J. Mulvaney, Vassilios A. Chouliaras

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

An efficient dual-mode floating-point Multiply-Add Fused Unit.

Konstantinos Manolopoulos, Dionysios I. Reisis, Vassilios A. Chouliaras

Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009

A configurable length, Fused Multiply-Add floating point unit for a VLIW processor.

Vassilios A. Chouliaras, Konstantinos Manolopoulos, Dionysios I. Reisis

Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Evaluating the performance of a configurable, extensible VLIW processor in FFT execution.

David Stevens, Nick Glynn, Panagiotis Galiatsatos, Vassilios A. Chouliaras, Dionysios I. Reisis

Proceedings of the 16th IEEE International Conference on Electronics, 2009

Efficient cascaded VLSI FFT architecture for OFDM systems.

Vassilios A. Chouliaras, Panagiotis Galiatsatos, Konstantinos Nakos, Dionysios I. Reisis, Nikolaos Vlassopoulos

Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008

A Novel Delta Sigma Control System Processor and Its VLSI Implementation.

Xiaofeng Wu, Vassilios A. Chouliaras, José L. Núñez-Yáñez, Roger M. Goodall

IEEE Trans. Very Large Scale Integr. Syst., 2008

Customization of an embedded RISC CPU with SIMD extensions for video encoding: A case study.

Vassilios A. Chouliaras, Vincent M. Dwyer, Shahrukh Agha, José L. Núñez-Yáñez, Dionysios I. Reisis, Konstantinos Nakos, Konstantinos Manolopoulos

Integr., 2008

A configurable and programmable motion estimation processor for the H.264 video codec.

José Luis Núñez-Yáñez, Eddie Hung, Vassilios A. Chouliaras

Proceedings of the FPL 2008, 2008

Feasibility of Imaging Photoplethysmography.

Jia Zheng, Sijung Hu, Vassilios A. Chouliaras, Ron Summers

Proceedings of the 2008 International Conference on BioMedical Engineering and Informatics, 2008

2007

Study of the Effects of SEU-Induced Faults on a Pipeline Protected Microprocessor.

Emmanuel Touloupis, James A. Flint, Vassilios A. Chouliaras, David D. Ward

IEEE Trans. Computers, 2007

Hardware implementation of a novel genetic algorithm.

Zhenhuan Zhu, David J. Mulvaney, Vassilios A. Chouliaras

Neurocomputing, 2007

High Performance 16K, 64K, 256K complex points VLSI Systolic FFT Architectures.

Konstantinos Manolopoulos, Konstantinos Nakos, Dionysios I. Reisis, Nikolaos Vlassopoulos, Vassilios A. Chouliaras

Proceedings of the 14th IEEE International Conference on Electronics, 2007

A Transmission Line Modelling VLSI processor designed with a novel Electronic System Level Methodology.

Vassilios A. Chouliaras, James A. Flint, Yibin Li

Proceedings of the 14th IEEE International Conference on Electronics, 2007

Dynamic Voltage Scaling in a FPGA-based System-on-Chip.

José L. Núñez-Yáñez, Vassilios A. Chouliaras, Jiri Gaisler

Proceedings of the FPL 2007, 2007

2006

Hardware assisted rate distortion optimization with embedded CABAC accelerator for the H.264 advanced video codec.

José L. Núñez-Yáñez, Vassilios A. Chouliaras, Daniele Alfonso, Fabrizio S. Rovati

IEEE Trans. Consumer Electron., 2006

Thread-parallel MPEG-2, MPEG-4 and H.264 video encoders for SoC multi-processor architectures.

Tom R. Jacobs, Vassilios A. Chouliaras, David J. Mulvaney

IEEE Trans. Consumer Electron., 2006

SystemC-defined SIMD instructions for high performance SoC architectures.

Vassilios A. Chouliaras, Konstantia Koutsomyti, Tom R. Jacobs, Simon Parr, David J. Mulvaney, Robert Thomson

Proceedings of the 13th IEEE International Conference on Electronics, 2006

A High Performance VLSI FFT Architecture.

Konstantinos Babionitakis, Konstantinos Manolopoulos, Konstantinos Nakos, Dionysios I. Reisis, Nikolaos Vlassopoulos, Vassilios A. Chouliaras

Proceedings of the 13th IEEE International Conference on Electronics, 2006

Investigation Of A New Genetic Algorithm Designed For System-On-Chip Realization.

Zhenhuan Zhu, David J. Mulvaney, Vassilios A. Chouliaras

Proceedings of the IEEE International Conference on Evolutionary Computation, 2006

A Novel Processor Architecture for Real-Time Control.

Xiaofeng Wu, Vassilios A. Chouliaras, José L. Núñez-Yáñez, Roger Goodall, Tanya Vladimirova

Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006

2005

Parallelism and the software-hardware interface in embedded systems.

Vassilios A. Chouliaras

PhD thesis, 2005

High-performance arithmetic coding VLSI macro for the H264 video compression standard.

José L. Núñez-Yáñez, Vassilios A. Chouliaras

IEEE Trans. Consumer Electron., 2005

A multi-standard video accelerator based on a vector architecture.

Vassilios A. Chouliaras, José L. Núñez-Yáñez, David J. Mulvaney, Fabrizio S. Rovati, Daniele Alfonso

IEEE Trans. Consumer Electron., 2005

A Configurable Statistical Lossless Compression Core Based on Variable Order Markov Modeling and Arithmetic Coding.

José L. Núñez-Yáñez, Vassilios A. Chouliaras

IEEE Trans. Computers, 2005

Applying data-parallel and scalar optimizations for the efficient implementation of the G.729A and G.723.1 speech coding standards.

Konstantia Koutsomyti, S. R. Parr, Vassilios A. Chouliaras, José L. Núñez-Yáñez

Proceedings of the Signal and Image Processing (SIP 2005), 2005

Configurable Multiprocessors for High-Performance MPEG-4 Video Coding.

Vassilios A. Chouliaras, Tom R. Jacobs, Ashwin K. Kumaraswamy, José L. Núñez-Yáñez

Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Design and Implementation of a High-Performance and Silicon Efficient Arithmetic Coding Accelerator for the H.264 Advanced Video Codec.

José L. Núñez-Yáñez, Vassilios A. Chouliaras

Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

Reduced-Bit, Full Search Block-Matching Algorithms and Their Hardware Realizations.

Vincent M. Dwyer, Shahrukh Agha, Vassilios A. Chouliaras

Proceedings of the Advanced Concepts for Intelligent Vision Systems, 2005

On the Performance Improvement of Sub-sampling MPEG-2 Motion Estimation Algorithms with Vector/SIMD Architectures.

Vassilios A. Chouliaras, Vincent M. Dwyer, Shahrukh Agha

Proceedings of the Advanced Concepts for Intelligent Vision Systems, 2005

2004

Three novel low complexity scanning orders for MPEG-2 full search motion estimation.

Christos Grecos, Azilah Saparon, Vassilios A. Chouliaras

Real Time Imaging, 2004

An application-specific processor hard macro for real-time control.

Xiaofeng Wu, Vassilios A. Chouliaras, Roger Goodall

Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

2003

Scalar coprocessors for accelerating the G723.1 and G729A speech coders.

Vassilios A. Chouliaras, José L. Núñez-Yáñez

IEEE Trans. Consumer Electron., 2003

A code compression scheme for improving SoC performance.

E. G. Nikolova, David J. Mulvaney, Vassilios A. Chouliaras, José L. Núñez-Yáñez

Proceedings of the 2003 International Symposium on System-on-Chip, 2003