Kshitij Raj

Orcid: 0000-0001-9160-5838

According to our database1, Kshitij Raj authored at least 10 papers between 2021 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
SENTRY: Protecting System-on-Chip Designs against Supply-Chain Attacks.
ACM Trans. Embed. Comput. Syst., May, 2026

2025
Security Enclave Architecture for Heterogeneous Security Primitives for Supply-Chain Attacks.
CoRR, July, 2025

2024
System-on-Chip Information Flow Validation Under Asynchronous Resets.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2024

Trimming The Fat: A Minimum-Security Architecture for Protecting SoC Designs Against Supply Chain Threats.
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

2023
SeVNoC: Security Validation of System-on-Chip Designs With NoC Fabrics.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023

2022
SoCCom: Automated Synthesis of System-on-Chip Architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2022

2021
The Curious Case of Trusted IC Provisioning in Untrusted Testing Facilities.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

CASTLE: Architecting Assured System-on-Chip Firmware Integrity.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

SoCCAR: Detecting System-on-Chip Security Violations Under Asynchronous Resets.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

SSEL: An Extensible Specification Language for SoC Security.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2021


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