Kumar N. Dwarakanath

According to our database1, Kumar N. Dwarakanath authored at least 9 papers between 2000 and 2006.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2006
Defect Modeling Using Fault Tuples.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

A reconfigurable design-for-debug infrastructure for SoCs.
Proceedings of the 43rd Design Automation Conference, 2006

2004
Generalized Sensitization using Fault Tuples.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Compact Dictionaries for Diagnosis of Unmodeled Faults in Scan-BIST.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

2003
Analyzing the Effectiveness of Multiple-Detect Test Sets.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002
Exploiting Dominance and Equivalence using Fault Tuples.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Fault Tuples in Diagnosis of Deep-Submicron Circuits.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2000
Universal test generation using fault tuples.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Universal fault simulation using fault tuples.
Proceedings of the 37th Conference on Design Automation, 2000


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