Lambert Schaelicke

According to our database, Lambert Schaelicke authored at least 16 papers between 1997 and 2009.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2009

Revisiting Cache Block Superloading.

Matthew A. Watkins, Sally A. McKee, Lambert Schaelicke

Proceedings of the High Performance Embedded Architectures and Compilers, 2009

2007

A Phase-Adaptive Approach to Increasing Cache Performance.

Matthew A. Watkins, Sally A. McKee, Lambert Schaelicke

Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007

2006

Design Trade-Offs for User-Level I/O Architectures.

Lambert Schaelicke, Alan L. Davis

IEEE Trans. Computers, 2006

The design and utility of the ML-RSIM system simulator.

Lambert Schaelicke, Michael A. Parker

J. Syst. Archit., 2006

2005

Evaluating the impact of the simulation environment on experimentation results.

Lambert Schaelicke

Perform. Evaluation, 2005

SPANIDS: a scalable network intrusion detection loadbalancer.

Lambert Schaelicke, Kyle B. Wheeler, Curt Freeland

Proceedings of the Second Conference on Computing Frontiers, 2005

2004

Cache implications of aggressively pipelined high performance microprocessors.

Timothy J. Dysart, Branden J. Moore, Lambert Schaelicke, Peter M. Kogge

Proceedings of the 2004 IEEE International Symposium on Performance Analysis of Systems and Software, 2004

2003

Characterizing the Performance of Network Intrusion Detection Sensors.

Lambert Schaelicke, Thomas Slabach, Branden J. Moore, Curt Freeland

Proceedings of the Recent Advances in Intrusion Detection, 6th International Symposium, 2003

Profiling Interrupt Handler Performance through Kernel Instrumentation.

Branden J. Moore, Thomas Slabach, Lambert Schaelicke

Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

2001

Architectural Support of User-Level Input/Output.

Lambert Schaelicke

PhD thesis, 2001

The Impulse Memory Controller.

Lixin Zhang, Zhen Fang, Michael A. Parker, Binu K. Mathew, Lambert Schaelicke, John B. Carter, Wilson C. Hsieh, Sally A. McKee

IEEE Trans. Computers, 2001

2000

Profiling I/O Interrupts in Modern Architectures.

Lambert Schaelicke, Al Davis, Sally A. McKee

Proceedings of the MASCOTS 2000, Proceedings of the 8th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, 29 August, 2000

1999

Impulse: Building a Smarter Memory Controller.

John B. Carter, Wilson C. Hsieh, Leigh Stoller, Mark R. Swanson, Lixin Zhang, Erik Brunvand, Al Davis, Chen-Chi Kuo, Ravindra Kuramkote, Michael A. Parker, Lambert Schaelicke, Terry Tateyama

Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, 1999

1998

Improving I/O Performance with a Conditional Store Buffer.

Lambert Schaelicke, Al Davis

Proceedings of the 31st Annual IEEE/ACM International Symposium on Microarchitecture, 1998

Memory System Support for Irregular Applications.

John B. Carter, Wilson C. Hsieh, Mark R. Swanson, Lixin Zhang, Erik Brunvand, Al Davis, Chen-Chi Kuo, Ravindra Kuramkote, Michael A. Parker, Lambert Schaelicke, Leigh Stoller, Terry Tateyama

Proceedings of the Languages, 1998

1997

ATOLL: A High-Performance Communication Device for Massively Parallel Systems.

Ulrich Brüning, Lambert Schaelicke

Proceedings of the 1997 Advances in Parallel and Distributed Computing Conference (APDC '97), 1997