Al Davis

Affiliations:
  • University of Utah, Salt Lake City, Utah, USA


According to our database1, Al Davis authored at least 68 papers between 1982 and 2023.

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Bibliography

2023
RETROSPECTIVE: Corona: System Implications of Emerging Nanophotonic Technology.
CoRR, 2023

2019
Practical and efficient incremental adaptive routing for HyperX networks.
Proceedings of the International Conference for High Performance Computing, 2019

Gen-Z Chipsetfor Exascale Fabrics.
Proceedings of the 2019 IEEE Hot Chips 31 Symposium (HCS), 2019

2018
SuperSim: Extensible Flit-Level Simulation of Large-Scale Interconnection Networks.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2018

2016
A unified memory network architecture for in-memory computing in commodity servers.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

2015
Memory Considerations for Low Energy Ray Tracing.
Comput. Graph. Forum, 2015

2014
Comparing Implementations of Near-Data Computing with In-Memory MapReduce Workloads.
IEEE Micro, 2014

NDC: Analyzing the impact of 3D-stacked memory+logic devices on MapReduce workloads.
Proceedings of the 2014 IEEE International Symposium on Performance Analysis of Systems and Software, 2014

MemZip: Exploring unconventional benefits from memory compression.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

2013
Quantifying the relationship between the power delivery network and architectural policies in a 3D-stacked memory device.
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

An Energy and Bandwidth Efficient Ray Tracing Architecture.
Proceedings of the High-Performance Graphics 2013, 2013

2012
Optical High Radix Switch Design.
IEEE Micro, 2012

Managing Data Placement in Memory Systems with Multiple Memory Controllers.
Int. J. Parallel Program., 2012

Fast, effective BVH updates for animated scenes.
Proceedings of the Symposium on Interactive 3D Graphics and Games, 2012

Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems.
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

Staged Reads: Mitigating the impact of DRAM writes on DRAM reads.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

The role of photonics in future data centers.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

2011
Asynchronous FUD.
IEEE Des. Test Comput., 2011

Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems.
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

The role of optics in future high radix switch design.
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

Prediction Based DRAM Row-Buffer Management in the Many-Core Era.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

CMOS Nanophotonics: Technology, System Implications, and a CMP Case Study.
Proceedings of the Low Power Networks-on-Chip., 2011

2010
Modeling NoC traffic locality and energy consumption with rent's communication probability distribution.
Proceedings of the International Workshop on System Level Interconnect Prediction Workshop, 2010

Rethinking DRAM design and organization for energy-constrained multi-cores.
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

Efficient MIMD architectures for high-performance ray tracing.
Proceedings of the 28th International Conference on Computer Design, 2010

Photonics and future datacenter networks.
Proceedings of the 2010 IEEE Hot Chips 22 Symposium, Stanford, CA, USA, August 22-24, 2010, 2010

Micro-pages: increasing DRAM efficiency with locality-aware data placement.
Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, 2010

Handling the problems and opportunities posed by multiple on-chip memory controllers.
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2009
HyperX: topology, routing, and packaging of efficient large-scale networks.
Proceedings of the ACM/IEEE Conference on High Performance Computing, 2009

StreamRay: a stream filtering architecture for coherent ray tracing.
Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems, 2009

2008
Fast ray tracing and the potential effects on graphics and gaming courses.
Comput. Graph., 2008

Corona: System Implications of Emerging Nanophotonic Technology.
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008

A Nanophotonic Interconnect for High-Performance Many-Core Computation.
Proceedings of the 16th Annual IEEE Symposium on High Performance Interconnects (HOTI 2008), 2008

2007
Rethinking graphics and gaming courses because of fast ray tracing.
Proceedings of the International Conference on Computer Graphics and Interactive Techniques, 2007

REFS Keynote: "Requirements for Services: Does it Make Sense?".
Proceedings of the 31st Annual International Computer Software and Applications Conference, 2007

Application driven embedded system design: a face recognition case study.
Proceedings of the 2007 International Conference on Compilers, 2007

2006
Design Trade-Offs for User-Level I/O Architectures.
IEEE Trans. Computers, 2006

2005
Keynote: Just Enough Requirements Management for Web Engineering.
Proceedings of the Web Engineering, 5th International Conference, 2005

2004
New Year's Resolutions for Software Quality.
IEEE Softw., 2004

Correct Embedded Computing Futures.
Proceedings of the Theorem Proving in Higher Order Logics, 17th International Conference, 2004

Energy efficient cluster co-processors [3G wireless applications].
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

A loop accelerator for low power embedded VLIW processors.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

A low power architecture for embedded perception.
Proceedings of the 2004 International Conference on Compilers, 2004

2003
Perception Coprocessors for Embedded Systems.
Proceedings of the First Workshop on Embedded Systems for Real-Time Multimedia, 2003

A low-power accelerator for the SPHINX 3 speech recognition system.
Proceedings of the International Conference on Compilers, 2003

2001
Requirements Triage: The Most Important Part of Software Engineeringand the Most Ignored.
Proceedings of the Thirteenth International Conference on Software Engineering & Knowledge Engineering (SEKE'2001), 2001

2000
Algorithmic foundations for a parallel vector access memory system.
Proceedings of the Twelfth annual ACM Symposium on Parallel Algorithms and Architectures, 2000

Profiling I/O Interrupts in Modern Architectures.
Proceedings of the MASCOTS 2000, Proceedings of the 8th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, 29 August, 2000

Design of a Parallel Vector Access Unit for SDRAM Memory Systems.
Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, 2000

1999
Impulse: Building a Smarter Memory Controller.
Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, 1999

1998
From The Editor: Recovering from Method Abuse.
IEEE Softw., 1998

Improving I/O Performance with a Conditional Store Buffer.
Proceedings of the 31st Annual IEEE/ACM International Symposium on Microarchitecture, 1998


1997
Efficient Communication Mechanisms for Cluster Based Parallel Computing.
Proceedings of the Communication and Architectural Support for Network-Based Parallel Computing, 1997

1996
Components of Congestion Control.
Proceedings of the 8th Annual ACM Symposium on Parallel Algorithms and Architectures, 1996

1994
R2: A Damped Adaptive Router Design.
Proceedings of the Parallel Computer Routing and Communication, 1994

Colored Petri Net Methods for Performance Analysis of Scalable High-Speed Interconnects.
Proceedings of the MASCOTS '94, Proceedings of the Second International Workshop on Modeling, Analysis, and Simulation On Computer and Telecommunication Systems, January 31, 1994

1993
The Post Office experience: designing a large asynchronous chip.
Integr., 1993

Automatic Synthesis of Fast Compact Asynchronous Control Circuits.
Proceedings of the Asynchronous Design Methodologies, Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, Manchester, UK, 31 March, 1993

1992
Mayfly: A General-Purpose, Scalable, Parallel Processing Architecture.
LISP Symb. Comput., 1992

1987
The Architecture of FAIM-1.
Computer, 1987

1986
The Post Office-Communication Support for Distributed Ensemble Architectures.
Proceedings of the 6th International Conference on Distributed Computing Systems, 1986

1985
The Architecture of the FAIM-1 Symbolic Multiprocessing System.
Proceedings of the 9th International Joint Conference on Artificial Intelligence. Los Angeles, 1985

The FAIM-1 Symbolic Multiprocessing System.
Proceedings of the Spring COMPCON'85, 1985

1984
Transforming an Ada Program Unit to Silicon and Verifying Its Behavior in an Ada Environment: A first Experiment.
IEEE Softw., 1984

Transforming an Ada Program Unit to Silicon and Testing It in an Ada Environment.
Proceedings of the COMPCON'84, Digest of Papers, Twenty-Eighth IEEE Computer Society International Conference, San Francisco, California, USA, February 27, 1984

1982
Data Flow Program Graphs.
Computer, 1982


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