Gopalakrishnan Vijayan

According to our database1, Gopalakrishnan Vijayan authored at least 26 papers between 1982 and 1997.

Collaborative distances:
  • Dijkstra number2 of two.
  • Erdős number3 of two.

Timeline

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Bibliography

1997
Library-less synthesis for static CMOS combinational logic circuits.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Fast power loss calculation for digital static CMOS circuits.
Proceedings of the European Design and Test Conference, 1997

1995
PEPPER - a timing driven early floorplanner.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

1992
Optimized test application timing for AC test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Workload-Driven Floorplanning for MIPS Optimization.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

1991
A new method for floor planning using topological constraint reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Generalization of Min-Cut Partitioning to Tree Structures and Its Applications.
IEEE Trans. Computers, 1991

Planar topological routing of pad nets.
Integr., 1991

On an edge ranking problem of trees and graphs.
Discret. Appl. Math., 1991

Test Application Timing: The Unexplored Issue in AC Test.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

1990
Partitioning logic on graph structures to minimize routing cost.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

New algorithms for the rectilinear Steiner tree problem.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Layer assignment for multichip modules.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Pad minimization for planar routing of multiple power nets.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Floorplanning by Topological Constraint Reduction.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

1989
On VHV-routing in channels with irregular boundaries.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

Constructing the optimal rectilinear Steiner tree derivable from a minimum spanning tree.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

Min-cost Partitioning on a Tree Structure and Applications.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

A New Approach to the Rectilinear Steiner Tree Problem.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988
Optimal Node Ranking of Trees.
Inf. Process. Lett., 1988

1987
An improved edge bound on the interval number of a graph.
J. Graph Theory, 1987

1986
Geometry of Planar Graphs with Angles.
Proceedings of the Second Annual ACM SIGACT/SIGGRAPH Symposium on Computational Geometry, 1986

1985
Rectilinear Graphs and their Embeddings.
SIAM J. Comput., 1985

Worst case analysis of a graph coloring algorithm.
Discret. Appl. Math., 1985

1983
VLSI Layout as Programming.
ACM Trans. Program. Lang. Syst., 1983

1982
ALI: A procedural language to describe VLSI layouts.
Proceedings of the 19th Design Automation Conference, 1982


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