Lerong Cheng

According to our database1, Lerong Cheng authored at least 27 papers between 2004 and 2014.

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Bibliography

2014
Statistical timing and power analysis of VLSI considering non-linear dependence.
Integration, 2014

2012
Fourier Series Approximation for Max Operation in Non-Gaussian and Quadratic Statistical Static Timing Analysis.
IEEE Trans. VLSI Syst., 2012

Statistical Timing and Power Optimization of Architecture and Device for FPGAs.
TRETS, 2012

2010
An Analytical Congestion Model with Bounded-Bend Detours.
Journal of Circuits, Systems, and Computers, 2010

Design dependent process monitoring for back-end manufacturing cost reduction.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

On confidence in characterization and application of variation models.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Efficient Additive Statistical Leakage Estimation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

Physically justifiable die-level modeling of spatial variation in view of systematic across wafer variability.
Proceedings of the 46th Design Automation Conference, 2009

Accounting for non-linear dependence using function driven component analysis.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
A fast congestion estimator for routing with bounded detours.
Integration, 2008

Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability.
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

Non-Gaussian statistical timing analysis using second-order polynomial fitting.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Device and Architecture Cooptimization for FPGA Power Reduction.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Non-Linear Statistical Static Timing Analysis for Non-Gaussian Variation Sources.
Proceedings of the 44th Design Automation Conference, 2007

2006
Congestion estimation for hexagonal routing.
Int. J. Comput. Math., 2006

A combinatorial congestion estimation approach with generalized detours.
Computers & Mathematics with Applications, 2006

FPGA Performance Optimization Via Chipwise Placement Considering Process Variations.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

2005
Digital spectrum of a nonuniformly sampled two-dimensional signal and its reconstruction.
IEEE Trans. Instrumentation and Measurement, 2005

On Theoretical Upper Bounds for Routing Estimation.
J. UCS, 2005

Probabilistic Estimation for Routing Space.
Comput. J., 2005

A Hierachical Method for Wiring and Congestion Prediction.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

FPGA device and architecture evaluation considering process variations.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Device and architecture co-optimization for FPGA power reduction.
Proceedings of the 42nd Design Automation Conference, 2005

2004
Routability checking for three-dimensional architectures.
IEEE Trans. VLSI Syst., 2004

Congestion estimation for 3-D circuit architectures.
IEEE Trans. on Circuits and Systems, 2004

Congestion Estimation for 3D Routing.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

A fast congestion estimator for routing with bounded detours.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004


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