William N. N. Hung

According to our database1, William N. N. Hung authored at least 73 papers between 2001 and 2019.

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Bibliography

2019
A New Pairwise NPN Boolean Matching Algorithm Based on Structural Difference Signature.
Symmetry, 2019

A Group Algebraic Approach to NPN Classification of Boolean Functions.
Theory Comput. Syst., 2019

2018
Temporal Coverage Analysis for Dynamic Verification.
IEEE Trans. on Circuits and Systems, 2018

Challenges in Large FPGA-based Logic Emulation Systems.
Proceedings of the 2018 International Symposium on Physical Design, 2018

2017
A Canonical-Based NPN Boolean Matching Algorithm Utilizing Boolean Difference and Cofactor Signature.
IEEE Access, 2017

2016
Computing Affine Equivalence Classes of Boolean Functions by Group Isomorphism.
IEEE Trans. Computers, 2016

Uncertainty Model for Configurable Hardware/Software and Resource Partitioning.
IEEE Trans. Computers, 2016

2015
Scalable Verification of a Generic End-Around-Carry Adder for Floating-Point Units by Coq.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

A Quantitative Characterization of Cross Coverage.
IEEE Trans. Computers, 2015

A multipartite entanglement measure based on coefficient matrices.
Quantum Information Processing, 2015

A Synthesis Method of Quantum Reversible Logic Circuit Based on Elementary Qutrit Quantum Logic Gates.
Journal of Circuits, Systems, and Computers, 2015

Pareto optimal mapping for tile-based network-on-chip under reliability constraints.
Int. J. Comput. Math., 2015

2014
Symbolic Analysis of Programmable Logic Controllers.
IEEE Trans. Computers, 2014

Performance-driven assignment and mapping for reliable networks-on-chips.
Journal of Zhejiang University - Science C, 2014

A Case Study on Formal Analysis of an Automated Guided Vehicle System.
J. Applied Mathematics, 2014

Combining Symmetry Reduction with Generalized Symbolic Trajectory Evaluation.
Comput. J., 2014

Motion planning with Satisfiability Modulo Theories.
Proceedings of the 2014 IEEE International Conference on Robotics and Automation, 2014

2013
Bayesian-Network-Based Reliability Analysis of PLC Systems.
IEEE Trans. Industrial Electronics, 2013

Complete Boolean Satisfiability Solving Algorithms Based on Local Search.
J. Comput. Sci. Technol., 2013

A Transformation-Based Approach to Implication of GSTE Assertion Graphs.
J. Applied Mathematics, 2013

Reliable Node Clustering for Mobile Ad Hoc Networks.
J. Applied Mathematics, 2013

Optimizing communication in mobile ad hoc network clustering.
Computers in Industry, 2013

System reliability calculation based on the run-time analysis of ladder program.
Proceedings of the Joint Meeting of the European Software Engineering Conference and the ACM SIGSOFT Symposium on the Foundations of Software Engineering, 2013

Verification and Implementation of the Protocol Standard in Train Control System.
Proceedings of the 37th Annual IEEE Computer Software and Applications Conference, 2013

Exponential-Condition-Based Barrier Certificate Generation for Safety Verification of Hybrid Systems.
Proceedings of the Computer Aided Verification - 25th International Conference, 2013

Sequential dependency and reliability analysis of embedded systems.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Maxterm Covering for Satisfiability.
IEEE Trans. Computers, 2012

New strategies for reliability analysis of Programmable Logic Controllers.
Mathematical and Computer Modelling, 2012

Reliability Analysis of PLC Systems by Bayesian Network.
Proceedings of the Sixth International Conference on Software Security and Reliability, 2012

Uncertain Model and Algorithm for Hardware/Software Partitioning.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Reliable NoC Mapping Based on Scatter Search.
Proceedings of the Information Computing and Applications - Third International Conference, 2012

Complete SAT Solver Based on Set Theory.
Proceedings of the Information Computing and Applications - Third International Conference, 2012

2011
Realization and synthesis of reversible functions.
Theor. Comput. Sci., 2011

A novel formalization of symbolic trajectory evaluation semantics in Isabelle/HOL.
Theor. Comput. Sci., 2011

A novel fault diagnosis mechanism for wireless sensor networks.
Mathematical and Computer Modelling, 2011

Exploring structural symmetry automatically in symbolic trajectory evaluation.
Formal Methods in System Design, 2011

Mathematical analysis of stage-based programmable logic controller.
Computers & Mathematics with Applications, 2011

Domain-Driven Probabilistic Analysis of Programmable Logic Controllers.
Proceedings of the Formal Methods and Software Engineering, 2011

Enhanced symbolic simulation of a round-robin arbiter.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Combining Theorem Proving and Symbolic Trajectory Evaluation in THM&STE.
Proceedings of the Hardware and Software: Verification and Testing, 2011

2010
Integrating Evolutionary Computation with Abstraction Refinement for Model Checking.
IEEE Trans. Computers, 2010

Compositional Abstraction Refinement for Timed Systems.
Proceedings of the 4th IEEE International Symposium on Theoretical Aspects of Software Engineering, 2010

A Memetic Approach for Nanoscale Hybrid Circuit Cell Mapping.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Synthesizing hybrid quantum circuits without ancilla qudits.
Proceedings of the IEEE Congress on Evolutionary Computation, 2010

2009
Data mining based decomposition for assume-guarantee reasoning.
Proceedings of 9th International Conference on Formal Methods in Computer-Aided Design, 2009

2008
A fast congestion estimator for routing with bounded detours.
Integration, 2008

Minimal universal library for n×n reversible circuits.
Computers & Mathematics with Applications, 2008

Bi-Directional Synthesis of 4-Bit Reversible Circuits.
Comput. J., 2008

The probability logics for nanoscale inverterscascade.
Proceedings of the IEEE Congress on Evolutionary Computation, 2008

2007
Four-level realisation of 3-qubit reversible functions.
IET Computers & Digital Techniques, 2007

2006
Probabilistic optimization for FPGA board level routing problems.
IEEE Trans. on Circuits and Systems, 2006

Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Group Theory Based Synthesis of Binary Reversible Circuits.
Proceedings of the Theory and Applications of Models of Computation, 2006

A Constructive Algorithm for Reversible Logic Synthesis.
Proceedings of the IEEE International Conference on Evolutionary Computation, 2006

2005
Majority-based reversible logic gates.
Theor. Comput. Sci., 2005

Bi-Direction Synthesis for Reversible Circuits.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Segmented channel routing with pin rearrangements via satisfiability.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Exact Synthesis of 3-Qubit Quantum Circuits from Non-Binary Quantum Gates Using Multiple-Valued Logic and Group Theory.
Proceedings of the 2005 Design, 2005

Implication of assertion graphs in GSTE.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Fast synthesis of exact minimal reversible circuits using group theory.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Routability checking for three-dimensional architectures.
IEEE Trans. VLSI Syst., 2004

Segmented channel routability via satisfiability.
ACM Trans. Design Autom. Electr. Syst., 2004

Congestion estimation for 3-D circuit architectures.
IEEE Trans. on Circuits and Systems, 2004

A comparative study on search strategies for cell assignments.
Int. J. Comput. Math., 2004

Congestion Estimation for 3D Routing.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Reference model based RTL verification: an integrated approach.
Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

Quantum logic synthesis by symbolic reachability analysis.
Proceedings of the 41th Design Automation Conference, 2004

2003
Board-level multiterminal net assignment for the partial cross-bar architecture.
IEEE Trans. VLSI Syst., 2003

2002
BDD minimization by scatter search.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

On segmented channel routability.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

On data address computation for embedded DSP systems.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Board-level multiterminal net assignment.
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

2001
BDD Variable Ordering by Scatter Search.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001


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