Proceedings of the Joint Meeting of the European Software Engineering Conference and the ACM SIGSOFT Symposium on the Foundations of Software Engineering, 2013

Verification and Implementation of the Protocol Standard in Train Control System.

[BibT_eX]

[DOI]

Yu Jiang

Proceedings of the 37th Annual IEEE Computer Software and Applications Conference, 2013

Exponential-Condition-Based Barrier Certificate Generation for Safety Verification of Hybrid Systems.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification - 25th International Conference, 2013

Sequential dependency and reliability analysis of embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

Maxterm Covering for Satisfiability.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2012

New strategies for reliability analysis of Programmable Logic Controllers.

[BibT_eX]

[DOI]

Math. Comput. Model., 2012

Reliability Analysis of PLC Systems by Bayesian Network.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Conference on Software Security and Reliability, 2012

Uncertain Model and Algorithm for Hardware/Software Partitioning.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Reliable NoC Mapping Based on Scatter Search.

[BibT_eX]

[DOI]

Proceedings of the Information Computing and Applications - Third International Conference, 2012

Complete SAT Solver Based on Set Theory.

[BibT_eX]

[DOI]

Proceedings of the Information Computing and Applications - Third International Conference, 2012

2011

Realization and synthesis of reversible functions.

[BibT_eX]

[DOI]

Theor. Comput. Sci., 2011

A novel formalization of symbolic trajectory evaluation semantics in Isabelle/HOL.

[BibT_eX]

[DOI]

Yongjian Li

William N. N. Hung

Xiaoyu Song

Theor. Comput. Sci., 2011

A novel fault diagnosis mechanism for wireless sensor networks.

[BibT_eX]

[DOI]

Math. Comput. Model., 2011

Exploring structural symmetry automatically in symbolic trajectory evaluation.

[BibT_eX]

[DOI]

Formal Methods Syst. Des., 2011

Mathematical analysis of stage-based programmable logic controller.

[BibT_eX]

[DOI]

Comput. Math. Appl., 2011

Domain-Driven Probabilistic Analysis of Programmable Logic Controllers.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods and Software Engineering, 2011

Enhanced symbolic simulation of a round-robin arbiter.

[BibT_eX]

[DOI]

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Combining Theorem Proving and Symbolic Trajectory Evaluation in THM&STE.

[BibT_eX]

[DOI]

Proceedings of the Hardware and Software: Verification and Testing, 2011

2010

Integrating Evolutionary Computation with Abstraction Refinement for Model Checking.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2010

Compositional Abstraction Refinement for Timed Systems.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Symposium on Theoretical Aspects of Software Engineering, 2010

A Memetic Approach for Nanoscale Hybrid Circuit Cell Mapping.

[BibT_eX]

[DOI]

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Synthesizing hybrid quantum circuits without ancilla qudits.

[BibT_eX]

[DOI]

Proceedings of the IEEE Congress on Evolutionary Computation, 2010

2009

Data mining based decomposition for assume-guarantee reasoning.

[BibT_eX]

[DOI]

Proceedings of 9th International Conference on Formal Methods in Computer-Aided Design, 2009

2008

A fast congestion estimator for routing with bounded detours.

[BibT_eX]

[DOI]

Integr., 2008

Minimal universal library for n×n reversible circuits.

[BibT_eX]

[DOI]

Comput. Math. Appl., 2008

Bi-Directional Synthesis of 4-Bit Reversible Circuits.

[BibT_eX]

[DOI]

Comput. J., 2008

The probability logics for nanoscale inverterscascade.

[BibT_eX]

[DOI]

Proceedings of the IEEE Congress on Evolutionary Computation, 2008

2007

Four-level realisation of 3-qubit reversible functions.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2007

Defect-Tolerant CMOL Cell Assignment via Satisfiability

[BibT_eX]

[DOI]

CoRR, 2007

2006

Probabilistic optimization for FPGA board level routing problems.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2006

Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Group Theory Based Synthesis of Binary Reversible Circuits.

[BibT_eX]

[DOI]

Proceedings of the Theory and Applications of Models of Computation, 2006

A Constructive Algorithm for Reversible Logic Synthesis.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Evolutionary Computation, 2006

2005

Majority-based reversible logic gates.

[BibT_eX]

[DOI]

Theor. Comput. Sci., 2005

Bi-Direction Synthesis for Reversible Circuits.

[BibT_eX]

[DOI]

Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Segmented channel routing with pin rearrangements via satisfiability.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Exact Synthesis of 3-Qubit Quantum Circuits from Non-Binary Quantum Gates Using Multiple-Valued Logic and Group Theory.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

Implication of assertion graphs in GSTE.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Fast synthesis of exact minimal reversible circuits using group theory.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Routability checking for three-dimensional architectures.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2004

Segmented channel routability via satisfiability.

[BibT_eX]

[DOI]

William N. N. Hung

Xiaoyu Song

El Mostapha Aboulhamid

Andrew A. Kennings

Alan J. Coppola

ACM Trans. Design Autom. Electr. Syst., 2004

Congestion estimation for 3-D circuit architectures.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2004

A comparative study on search strategies for cell assignments.

[BibT_eX]

[DOI]

Int. J. Comput. Math., 2004

Congestion Estimation for 3D Routing.

[BibT_eX]

[DOI]

Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Reference model based RTL verification: an integrated approach.

[BibT_eX]

[DOI]

William N. N. Hung

Naren Narasimhan

Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

Quantum logic synthesis by symbolic reachability analysis.

[BibT_eX]

[DOI]

Proceedings of the 41th Design Automation Conference, 2004

2003

Board-level multiterminal net assignment for the partial cross-bar architecture.

[BibT_eX]

[DOI]

Xiaoyu Song

William N. N. Hung

Alan Mishchenko

Malgorzata Chrzanowska-Jeske

Andrew A. Kennings

Alan J. Coppola

IEEE Trans. Very Large Scale Integr. Syst., 2003

2002

BDD minimization by scatter search.

[BibT_eX]

[DOI]

William N. N. Hung

Xiaoyu Song

El Mostapha Aboulhamid

Michael A. Driscoll

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

On segmented channel routability.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

On data address computation for embedded DSP systems.

[BibT_eX]

[DOI]

William N. N. Hung

Xiaoyu Song

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Board-level multiterminal net assignment.

[BibT_eX]

[DOI]

Xiaoyu Song

William N. N. Hung

Alan Mishchenko

Malgorzata Chrzanowska-Jeske

Alan J. Coppola

Andrew A. Kennings

Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

2001

BDD Variable Ordering by Scatter Search.

[BibT_eX]

[DOI]

William N. N. Hung

Xiaoyu Song

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

William N. N. Hung

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