Lioua Labrak

According to our database, Lioua Labrak authored at least 12 papers between 2007 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Artificial neural network-based solution for PSP MOSFET model card extraction.

Alba Ordonez Rodriguez, Fabien Gilibert, Francois Paolini, Pascal Urard, Roberto Guizzetti, John Samuel, Remy Cellier, Lioua Labrak, Bastien Deveautour

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2023

Reinforcement Learning for Analog Sizing Optimization.

Michel Chevalier, Severin Trochut, Roberto Guizzetti, Pascal Urard, Lioua Labrak, John Samuel, Remy Cellier, Nacer Abouchi

Proceedings of the 19th International Conference on Synthesis, 2023

2020

Fast hierarchical system synthesis based on predictive models.

Adil Brik, Lioua Labrak, Ian O'Connor, Daniel Saias

Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020

2019

Fast extraction of predictive models for integrated circuits using n-performance Pareto fronts.

Adil Brik, Lioua Labrak, Laurent Carrel, Ian O'Connor, Ramy Iskander

Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

A Low-Voltage Sub-ns Pulse Integrated CMOS Laser Diode Driver for SPAD-based Time-of-Flight Rangefinding in Mobile Applications.

Samuel Rigault, Nicolas Moeneclaey, Lioua Labrak, Ian O'Connor

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

2018

CMOS VCSEL driver dedicated for sub-nanosecond laser pulses generation in SPAD-based time-of-flight rangefinder.

Samuel Rigault, Nicolas Moeneclaey, Lioua Labrak, Ian O'Connor

Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

2014

Hierarchical design flow for heterogenous systems using Pareto front interpolation.

Lioua Labrak, Ian O'Connor, Felipe Frantz

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2012

3D IC floorplanning: Automating optimization settings and exploring new thermal-aware management techniques.

Felipe Frantz, Lioua Labrak, Ian O'Connor

Microelectron. J., 2012

Optimization based on surrogate modeling for analog integrated circuits.

Firas Yengui, Lioua Labrak, Patrice Russo, Felipe Frantz, Nacer Abouchi

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011

3D-IC floorplanning: Applying meta-optimization to improve performance.

Felipe Frantz, Lioua Labrak, Ian O'Connor

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

2010

Bottom-up Verification Methodology for CMOS Photonic Linear Heterogeneous System.

Bo Wang, Ian O'Connor, Emmanuel Drouard, Lioua Labrak

Proceedings of the 2010 Forum on specification & Design Languages, 2010

2007

Automated cost function formulation for analog design optimization.

Lioua Labrak, T. Tixier, Y. Fellah, Nacer Abouchi

Proceedings of the 18th European Conference on Circuit Theory and Design, 2007