Ian O'Connor

According to our database1, Ian O'Connor authored at least 120 papers between 2000 and 2020.

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Bibliography

2020
3D logic cells design and results based on Vertical NWFET technology including tied compact model.
CoRR, 2020

Fast hierarchical system synthesis based on predictive models.
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020

Exploiting Approximate Computing for implementing Low Cost Fault Tolerance Mechanisms.
Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020

Sensitivity Analysis and Compression Opportunities in DNNs Using Weight Sharing.
Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2020

On the Automatic Exploration of Weight Sharing for Deep Neural Network Compression.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Emerging Neural Workloads and Their Impact on Hardware.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Thermal-Aware Design Method for Laser Group Control in Nanophotonic Interconnects.
IEEE Trans. Very Large Scale Integr. Syst., 2019

A comprehensive compact model for the design of all-spin-logic based circuits.
Microelectron. J., 2019

Guest Editors' Introduction: Emerging Networks-on-Chip Designs, Technologies, and Applications.
ACM J. Emerg. Technol. Comput. Syst., 2019

Fast extraction of predictive models for integrated circuits using n-performance Pareto fronts.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

A Low-Voltage Sub-ns Pulse Integrated CMOS Laser Diode Driver for SPAD-based Time-of-Flight Rangefinding in Mobile Applications.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

Rebooting Computing: The Challenges for Test and Reliability.
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

2018
Guest Editorial: Emerging Technologies and Architectures for Manycore Computing Part 1: Hardware Techniques.
IEEE Trans. Multi Scale Comput. Syst., 2018

Towards Maximum Energy Efficiency in Nanophotonic Interconnects with Thermal-Aware On-Chip Laser Tuning.
IEEE Trans. Emerg. Top. Comput., 2018

Offline Optimization of Wavelength Allocation and Laser Power in Nanophotonic Interconnects.
ACM J. Emerg. Technol. Comput. Syst., 2018

Prospects for energy-efficient edge computing with integrated HfO2-based ferroelectric devices.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

CMOS VCSEL driver dedicated for sub-nanosecond laser pulses generation in SPAD-based time-of-flight rangefinder.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

Systematic Design Method of Passive Ladder Filters using a Generalised Variable.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

Run-Time management of energy-performance trade-off in Optical Network-on-Chip.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

Computing with ferroelectric FETs: Devices, models, systems, and applications.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Large scale, high density integration of all spin logic.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Energy-Efficiency Comparison of Multi-Layer Deposited Nanophotonic Crossbar Interconnects.
ACM J. Emerg. Technol. Comput. Syst., 2017

Arithmetic Logic Unit based on all-spin logic devices.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

An Energy-Efficient Reconfigurable Nanophotonic Computing Architecture Design: Optical Lookup Table.
Proceedings of the IEEE International Conference on Rebooting Computing, 2017

Hybrid Topologies for Reconfigurable Matrices Based on Nano-Grain Cells.
Proceedings of the IEEE International Conference on Rebooting Computing, 2017

Performance and energy aware wavelength allocation on ring-based WDM 3D optical NoC.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Energy and Performance Trade-off in Nanophotonic Interconnects using Coding Techniques.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Foreword.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

2015
An efficient and simple compact modeling approach for 3-D interconnects with IC's stack global electrical context consideration.
Microelectron. J., 2015

Multi-Level Mapping of Nanocomputer Architectures Based on Hardware Reuse.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

Full-adder circuit design based on all-spin logic device.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

Communication Aware Design Method for Optical Network-on-Chip.
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

Multilevel Modeling Methodology for Reconfigurable Computing Systems Based on Silicon Photonics.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Channel Allocation Protocol for Reconfigurable Optical Network-on-Chip.
Proceedings of the 2015 Workshop on Exploiting Silicon Photonics for Energy-Efficient High Performance Computing, 2015

Fast optical simulation from a reduced set of impulse responses using SystemC-AMS.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Thermal aware design method for VCSEL-based on-chip optical interconnect.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

LVS check for photonic integrated circuits: curvilinear feature extraction and validation.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Complementary communication path for energy efficient on-chip optical interconnects.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Energy-efficient optical crossbars on chip with multi-layer deposited silicon.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Modeling and simulation of networked low-power embedded systems: a taxonomy.
EURASIP J. Wirel. Commun. Netw., 2014

Optical crossbars on chip, a comparative study based on worst-case losses.
Concurr. Comput. Pract. Exp., 2014

Complementary logic interface for high performan optical computing with OLUT.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

Silicon photonics design rule checking: Application of a programmable modeling engine for non-Manhattan geometry verification.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

A reconfigurable optical network on chip for streaming applications.
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014

Hierarchical design flow for heterogenous systems using Pareto front interpolation.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Chameleon: Channel efficient Optical Network-on-Chip.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Functions classification approach to generate reconfigurable fine-grain logic based on Ambipolar Independent Double Gate FET (Am-IDGFET).
Microelectron. J., 2013

Reduction methods for adapting optical network on chip topologies to 3D architectures.
Microprocess. Microsystems, 2013

iMASKO: A Genetic Algorithm Based Optimization Framework for Wireless Sensor Networks.
J. Sens. Actuator Networks, 2013

Reconfigurable photonic switching: Towards all-optical FPGAs.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Energy Performance of High Data Rate and Low Power Transceiver based Wireless Body Area Networks.
Proceedings of the SENSORNETS 2013, 2013

Performance evaluations of unslotted CSMA/CA algorithm at high data rate WSNs scenario.
Proceedings of the 2013 9th International Wireless Communications and Mobile Computing Conference, 2013

Potential and pitfalls of silicon photonics computing and interconnect.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Energy Measurements and Evaluations on High Data Rate and Ultra Low Power WSN Node.
Proceedings of 10th IEEE International Conference on Networking, Sensing and Control, 2013

Optical look up table.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Analog IC Variability Bound Estimation Using the Cornish-Fisher Expansion.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

3D IC floorplanning: Automating optimization settings and exploring new thermal-aware management techniques.
Microelectron. J., 2012

A cycle-accurate transaction-level modelled energy simulation approach for heterogeneous Wireless Sensor Networks.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012

Ambipolar independent double gate FET logic.
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

Low-power design technique with ambipolar double gate devices.
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

Ambipolar double gate CNTFETs based reconfigurable logic cells.
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

Ambipolar double-gate FETs for the design of compact logic structures.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

2011
Matrix Nanodevice-Based Logic Architectures and Associated Functional Mapping Method.
ACM J. Emerg. Technol. Comput. Syst., 2011

IDEA1: A validated SystemC-based system-level design and simulation environment for wireless sensor networks.
EURASIP J. Wirel. Commun. Netw., 2011

Reprogramming hardware-software heterogeneous Wireless Sensor Networks.
Proceedings of the 14th International Symposium on Wireless Personal Multimedia Communications, 2011

3D-IC floorplanning: Applying meta-optimization to improve performance.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Layout guidelines for 3D architectures including Optical Ring Network-on-Chip (ORNoC).
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Multi-objective mapping for matrix-based nanocomputer architectures.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

Using Self-Reconfiguration to Increase Manufacturing Yield of CNTFET-based Architectures.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

Ambipolar double-gate FET binary-decision- diagram (Am-BDD) for reconfigurable logic cells.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

Ultra-fine grain FPGAs: A granularity study.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

IDEA1: A Validated System C-Based Simulator for Wireless Sensor Networks.
Proceedings of the IEEE 8th International Conference on Mobile Adhoc and Sensor Systems, 2011

Evaluation of a crossbar multiplexer in a lithography-based nanowire technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

High performance 4: 1 multiplexer with ambipolar double-gate FETs.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

Fine-grain reconfigurable logic cells based on double-gate CNTFETs.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Multi-granularity thermal evaluation of 3D MPSoC architectures.
Proceedings of the Design, Automation and Test in Europe, 2011

Optical Ring Network-on-Chip (ORNoC): Architecture and design methodology.
Proceedings of the Design, Automation and Test in Europe, 2011

Can we go towards true 3-D architectures?
Proceedings of the 48th Design Automation Conference, 2011

2010
ULPFA: A New Efficient Design of a Power-Aware Full Adder.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Multi-Optical Network-on-Chip for Large Scale MPSoC.
IEEE Embed. Syst. Lett., 2010

Performance evaluation for passive-type Optical network-on-chip.
Proceedings of the 21st IEEE International Symposium on Rapid System Prototyping, 2010

Reducing transistor count in clocked standard cells with ambipolar double-gate FETs.
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010

Optical network-on-chip reconfigurable model for multi-level analysis.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Logic cells and interconnect strategies for nanoscale reconfigurable computing fabrics.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Phase-change-memory-based storage elements for configurable logic.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Bottom-up Verification Methodology for CMOS Photonic Linear Heterogeneous System.
Proceedings of the 2010 Forum on specification & Design Languages, 2010

2009
Modeling and Formal Verification of a Passive Optical Network on Chip Behavior.
Electron. Commun. Eur. Assoc. Softw. Sci. Technol., 2009

Emerging Technologies and Nanoscale Computing Fabrics.
Proceedings of the VLSI-SoC: Technologies for Systems Integration, 2009

Interconnection scheme and associated mapping method of reconfigurable cell matrices based on nanoscale devices.
Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures, 2009

Mapping method of reconfigurable cell matrices based on nanoscale devices using inter-stage fixed interconnection scheme.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

Reconfigurable nanoscale logic cells : a comparison study.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

Optical NoC design-parameters exploration and analysis.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008
Fine-Grain Reconfigurable Logic Cells Based on Double-Gate MOSFETs.
Proceedings of the VLSI-SoC: Design Methodologies for SoC and SiP, 2008

2007
Systematic Simulation-Based Predictive Synthesis of Integrated Optical Interconnect.
IEEE Trans. Very Large Scale Integr. Syst., 2007

CNTFET Modeling and Reconfigurable Logic-Circuit Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

A Family of Ultra-Fine Grain CNTFET-based Reconfigurable Logic Gates.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

Design of a Novel CNTFET-based Reconfigurable Logic Gate.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Ultra-fine grain reconfigurability using CNTFETs.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

Towards the High-Level Design of Optical Networks-on-Chip. Formalization of Opto-Electrical Interfaces.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

Heterogeneous systems on chip and systems in package.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

System level assessment of an optical NoC in an MPSoC platform.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Novel CNTFET-based Reconfigurable Logic Gate Design.
Proceedings of the 44th Design Automation Conference, 2007

2005
Heterogeneous Modelling of an Optical Network-on-Chip with SystemC.
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005

Towards reconfigurable optical networks on chip.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005

UML/XML based approach to hierarchical AMS Synthesis.
Proceedings of the Forum on specification and Design Languages, 2005

VHDL & VHDL-AMS Modelling and Simulation of a CMOS Imager IP.
Proceedings of the Forum on specification and Design Languages, 2005

2004
Optical solutions for system-level interconnect.
Proceedings of the Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), 2004

Simulation of Electrical and Optical Interconnections for Future VLSI ICs.
Proceedings of the Computational Science, 2004

Optical Network On-chip Multi-Domain modeling using SystemC.
Proceedings of the Forum on specification and Design Languages, 2004

RUNE: Platform for Automated Design of Integrated Multi-Domain Systems. Application to High-Speed CMOS Photoreceiver Front-Ends.
Proceedings of the 2004 Design, 2004

Extremely Low-Power Logic.
Proceedings of the 2004 Design, 2004

Design and Behavioral Modeling Tools for Optical Network-on-Chip.
Proceedings of the 2004 Design, 2004

On-Chip Optical Interconnect for Low-Power.
Proceedings of the Ultra Low-Power Electronics and Design, 2004

2003
Design Methodologies for High-Speed CMOS Photoreceiver Front-Ends.
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

Optical versus Electrical Interconnections for Clock Distribution Networks in New VLSI Technologies.
Proceedings of the Integrated Circuit and System Design, 2003

Predictive design space exploration of maximum bandwidth CMOS photoreceiver preamplifiers.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

Hierarchical synthesis of high-speed CMOS photoreceiver front-ends using a multi-domain behavioural description language.
Proceedings of the Forum on specification and Design Languages, 2003

A VHDL-AMS library of hierarchical optoelectronic device models.
Proceedings of the Forum on specification and Design Languages, 2003

2000
Automated synthesis of current-memory cells.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Design and Optimization of Optical Links Based on VHDL-AMS Modeling.
Proceedings of the 2000 IEEE/ACM International Workshop on Behavioral Modeling and Simulation, 2000


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