Bastien Deveautour

According to our database1, Bastien Deveautour authored at least 19 papers between 2016 and 2024.

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Bibliography

2024
SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN Accelerators.
CoRR, 2024

Artificial neural network-based solution for PSP MOSFET model card extraction.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2023
A Fault Injection Framework for AI Hardware Accelerators.
Proceedings of the 24th IEEE Latin American Test Symposium, 2023

Energy-efficient Computation-In-Memory Architecture using Emerging Technologies.
Proceedings of the International Conference on Microelectronics, 2023

Input-aware accuracy characterization for approximate circuits.
Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2023

Investigating the effect of approximate multipliers on the resilience of a systolic array DNN accelerator.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

Resilience-Performance Tradeoff Analysis of a Deep Neural Network Accelerator.
Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023

2022
Exploiting Approximate Computing for Efficient and Reliable Convolutional Neural Networks.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

Dependability of Alternative Computing Paradigms for Machine Learning: hype or hope?
Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022

Input-Aware Approximate Computing.
Proceedings of the IEEE International Conference on Automation, 2022

Test and Reliability of Approximate Hardware.
Proceedings of the Approximate Computing, 2022

2021
Reducing Overprovision of Triple Modular Reduncancy Owing to Approximate Computing.
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021

Emerging Computing Devices: Challenges and Opportunities for Test and Reliability<sup>*</sup>.
Proceedings of the 26th IEEE European Test Symposium, 2021

2020
On Using Approximate Computing to Build an Error Detection Scheme for Arithmetic Circuits.
J. Electron. Test., 2020

Development and Application of Embedded Test Instruments to Digital, Analog/RFs and Secure ICs.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

QAMR: an Approximation-Based Fully Reliable TMR Alternative for Area Overhead Reduction.
Proceedings of the IEEE European Test Symposium, 2020

2018
Is aproximate computing suitable for selective hardening of arithmetic circuits?
Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018

2017
A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits.
J. Electron. Test., 2017

2016
A low-cost susceptibility analysis methodology to selectively harden logic circuits.
Proceedings of the 21th IEEE European Test Symposium, 2016


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