Massimo Alioto
Orcid: 0000-0002-4127-8258
According to our database1,
Massimo Alioto
authored at least 299 papers
between 1998 and 2024.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2016, "For contributions to energy-efficient VLSI circuits".
Timeline
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On csauthors.net:
Bibliography
2024
Picowatt-Power Super-Cutoff Analog Building Blocks and 78-pW Battery-Less Wake-Up Receiver for Light-Harvested Near-Always-On Operation.
IEEE J. Solid State Circuits, April, 2024
Guest Editorial Introduction to the Special Section on the 2023 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits, January, 2024
6.3 Imager with In-Sensor Event Detection and Morphological Transformations with 2.9pJ/pixel×frame Object Segmentation FOM for Always-On Surveillance in 40nm.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
Laser Voltage Probing Attack Detection With 100% Area/Time Coverage at Above/Below the Bandgap Wavelength and Fully-Automated Design.
IEEE J. Solid State Circuits, October, 2023
Capacitance-to-Digital Converter for Harvested Systems Down to 0.3 V With No Trimming, Reference, and Voltage Regulation.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2023
Opening of the 2023 Editorial Year - This Coda as Prelude of Next TVLSI Cycle With Sustained Growth.
IEEE Trans. Very Large Scale Integr. Syst., 2023
IEEE J. Solid State Circuits, 2023
Voltage Reference With Corner-Aware Replica Selection/Merging for 1.4-mV Accuracy in Harvested Systems Down to 3.9 pW, 0.2 V.
IEEE Access, 2023
Self-Referenced Design-Agnostic Laser Voltage Probing Attack Detection with 100% Protection Coverage, 58% Area Overhead for Automated Design.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Visual Content-Agnostic Novelty Detection Engine with 2.4 pJ/pixel Energy and Two-Order of Magnitude DNN Activity Reduction in 40 nm.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
38.4-pW, 0.14-mm<sup>2</sup> Body-Driven Temperature-to-Digital Converter and Voltage Reference with 0.6-1.6-V Unregulated Supply for Battery-Less Systems.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Voltage Scaling-Agnostic Counteraction of Side-Channel Neural Net Reverse Engineering via Machine Learning Compensation and Multi-Level Shuffling.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
ECC-Less Multi-Level SRAM Physically Unclonable Function and 127% PUF-to-Memory Capacity Ratio with No Bitcell Modification in 28nm.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Super-Cutoff Analog Building Blocks for pW/Stage Operation and Demonstration of 78-pW Battery-Less Light-Harvested Wake-Up Receiver down to Moonlight.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
55pW/pixel Peak Power Imager with Near-Sensor Novelty/Edge Detection and DC-DC Converter-Less MPPT for Purely Harvested Sensor Nodes.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 0.4V 12b Comparator Offset Injection Assisted SAR ADC achieving 0.425 fJ/conv-step.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
Single-Antenna Backscattered BLE5 Transmitter with up to 97m Range, 10.6 μW Peak Power for Purely-Harvested Green Systems.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
A Resistor/Trimming-Less Self-Biased Current Reference Class with Area Down to $3,500\ \mu \mathrm{m}^{2}$, 42.8 pW Power and 10.4% Accuracy across Corner Wafers in 180 nm.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
Temporal Similarity-Based Computation Reduction for Video Transformers in Edge Camera Nodes.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
Editorial Opening of the 2022 TVLSI Editorial Year - Connecting Trends From Society to VLSI Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2022
IEEE J. Solid State Circuits, 2022
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
On-Chip Laser Voltage Probing Attack Detection with 100% Area Coverage at Above/Below the Bandgap Wavelength and Fully-Automated Design.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Fully-Digital Broadband Calibration-Less Impedance Monitor for Probe Insertion Detection against Power Analysis Attacks.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Imager with Dynamic LSB Adaptation and Ratiometric Readout for Low-Bit Depth 5-μW Peak Power in Purely-Harvested Systems.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022
Conversion Time-Power Tradeoff in Capacitance-to-Digital Converters with Dual-Mode Logic.
Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022
Side-Channel Attack Counteraction via Machine Learning-Targeted Power Compensation for Post-Silicon HW Security Patching.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
Architecture for 3D Convolutional Neural Networks Based on Temporal Similarity Removal.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
From Less Batteries to Battery-Less: Enabling A Greener World through Ultra-Wide Power-Performance Adaptation down to pWs.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
Capacitance-Based Voltage Regulation- and Reference-Free Temperature-to-Digital Converter down to 0.3 V and 2.5 nW for Direct Harvesting.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
DDPMnet: All-Digital Pulse Density-Based DNN Architecture with 228 Gate Equivalents/MAC Unit, 28-TOPS/W and 1.5-TOPS/mm2 in 40nm.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
Temporal Redundancy-Based Computation Reduction for 3D Convolutional Neural Networks.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Rail-to-Rail Dynamic Voltage Comparator Scalable Down to pW-Range Power and 0.15-V Supply.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Design of Digital OTAs With Operation Down to 0.3 V and nW Power for Direct Harvesting.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE J. Solid State Circuits, 2021
PUF Architecture with Run-Time Adaptation for Resilient and Energy-Efficient Key Generation via Sensor Fusion.
IEEE J. Solid State Circuits, 2021
On-Chip Links With Energy-Quality Tradeoff in Error-Resilient and Machine Learning Applications.
IEEE J. Solid State Circuits, 2021
Sub-nW Microcontroller With Dual-Mode Logic and Self-Startup for Battery-Indifferent Sensor Nodes.
IEEE J. Solid State Circuits, 2021
±CIM SRAM for Signed In-Memory Broad-Purpose Computing From DSP to Neural Processing.
IEEE J. Solid State Circuits, 2021
Trimming-Less Voltage Reference for Highly Uncertain Harvesting Down to 0.25 V, 5.4 pW.
IEEE J. Solid State Circuits, 2021
TempDiff: Feature Map-Level CNN Sparsity Enhancement at Near-Zero Memory Overhead via Temporal Difference.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
From Less Batteries to Battery-Less Alert Systems with Wide Power Adaptation down to nWs - Toward a Smarter, Greener World.
IEEE Des. Test, 2021
Battery-Less IoT Sensor Node with PLL-Less WiFi Backscattering Communications in a 2.5-μW Peak Power Envelope.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Fully-Digital Self-Calibrating Decoder with Sub-µW, 1.6fJ/convstep and 0.0075mm<sup>2</sup> per Receptor for Scaling to Human-Like Tactile Sensing Density.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
36.1 Unified In-Memory Dynamic TRNG and Multi-Bit Static PUF Entropy Generation for Ubiquitous Hardware Security.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Session 36 Overview: Hardware Security Digital Architectures and Systems Subcommittee.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Capacitance-to-Digital Converter for Operation Under Uncertain Harvested Voltage down to 0.3V with No Trimming, Reference and Voltage Regulation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
STT-MRAM Architecture with Parallel Accumulator for In-Memory Binary Neural Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
SRAM with In-Memory Inference and 90% Bitline Activity Reduction for Always-On Sensing with 109 TOPS/mm<sup>2</sup> and 749-1, 459 TOPS/W in 28nm.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021
A 3.2-pW, 0.2-V Trimming-Less Voltage Reference with 1.4-mV Across-Wafer Total Accuracy.
Proceedings of the 47th ESSCIRC 2021, 2021
A 1448-Mpixel/s, 84-pJ/Pixel Display Stream Compression Encoder in 28 nm for 4K Video Resolution.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2021
TempDiff: Temporal Difference-Based Feature Map-Level Sparsity Induction in CNNs with <4% Memory Overhead.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
2020
Automated Design of Reconfigurable Microarchitectures for Accelerators Under Wide-Voltage Scaling.
IEEE Trans. Very Large Scale Integr. Syst., 2020
Editorial on the Conclusion of the 2020 Editorial Year - The Climactic Finale of a Peculiar Year.
IEEE Trans. Very Large Scale Integr. Syst., 2020
Editorial on the Opening of the New Editorial Year - The State of the IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2020
Low-Energy Voice Activity Detection via Energy-Quality Scaling From Data Conversion to Machine Learning.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020
Approximate Multipliers With Dynamic Truncation for Energy Reduction via Graceful Quality Degradation.
IEEE Trans. Circuits Syst., 2020
Integrated Power Management for Battery-Indifferent Systems With Ultra-Wide Adaptation Down to nW.
IEEE J. Solid State Circuits, 2020
Processor Energy-Performance Range Extension Beyond Voltage Scaling via Drop-In Methodologies.
IEEE J. Solid State Circuits, 2020
Energy-Quality Scalable Memory-Frugal Feature Extraction for Always-On Deep Sub-mW Distributed Vision.
IEEE Access, 2020
Fully Synthesizable Low-Area Analogue-to-Digital Converters With Minimal Design Effort Based on the Dyadic Digital Pulse Modulation.
IEEE Access, 2020
Multi-Sensor Platform with Five-Order-of-Magnitude System Power Adaptation down to 3.1nW and Sustained Operation under Moonlight Harvesting.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
A 0.25-V, 5.3-pW Voltage Reference with 25-μV/°C Temperature Coefficient, 140-μV/V Line Sensitivity and 2, 200-μm<sup>2</sup> Area in 180nm.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
Enabling Always-On Sensor Nodes Entirely Powered by Sustainable Energy Sources - Making Our World Smarter and Greener.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Voice Activity Detection with >83% Accuracy under SNR down to -3dB at $1.19\mu \mathrm{W}$ and 0.07mm<sup>2</sup> in 40nm.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
Editorial: TVLSI Keynote Papers Enriching Our Transactions With Invited Contributions.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Fully Synthesizable Low-Area Digital-to-Analog Converter With Graceful Degradation and Dynamic Power-Resolution Scaling.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
IEEE J. Solid State Circuits, 2019
IEEE J. Solid State Circuits, 2019
Token-Based Security for the Internet of Things With Dynamic Energy-Quality Tradeoff.
IEEE Internet Things J., 2019
Integrated Power Management and Microcontroller for Ultra-Wide Power Adaptation down to nW.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
Thursday Keynote: Survival of The Fittest: Circuits and Architectures for Computation with Wide Power- Performance Adaptation Beyond Voltage Scaling.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Energy-Quality Scalable Analog-to-Digital Conversion and Machine Learning Engine in a 51.9 nJ/frame Voice Activity Detector.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
An Energy Aware Variation-Tolerant Writing Termination Control for STT-based Non Volatile Flip-Flops.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
PUF-based Key Generation with Design Margin Reduction via In-Situ and PVT Sensor Fusion.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
Low-Swing Links with Dynamic Energy-Quality Trade-off for Error-Resilient Applications.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
Enabling Ubiquitous Hardware Security via Energy-Efficient Primitives and Systems : (Invited Paper).
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2018
A Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/STT-MTJ Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
iRazor: Current-Based Error Detection and Correction Scheme for PVT Variation in 40-nm ARM Cortex-R4 Processor.
IEEE J. Solid State Circuits, 2018
Fully Synthesizable PUF Featuring Hysteresis and Temperature Compensation for 3.2% Native BER and 1.02 fJ/b in 40 nm.
IEEE J. Solid State Circuits, 2018
Dynamically Adaptable Pipeline for Energy-Efficient Microarchitectures Under Wide Voltage Scaling.
IEEE J. Solid State Circuits, 2018
Integr., 2018
Energy-Quality Scalable Integrated Circuits and Systems: Continuing Energy Scaling in the Twilight of Moore's Law.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
Guest Editorial Energy-Quality Scalable Circuits and Systems for Sensing and Computing: From Approximate to Communication-Inspired and Learning-Based.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
Ultra-Low Power Crypto-Engine Based on Simon 32/64 for Energy- and Area-Constrained Integrated Systems.
CoRR, 2018
IEEE Consumer Electron. Mag., 2018
A Sub-Leakage PW-Power HZ-Range Relaxation Oscillator Operating with 0.3V-1.8V Unregulated Supply.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
A 595pW 14pJ/Cycle microcontroller with dual-mode standard cells and self-startup for battery-indifferent distributed sensing.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Design-Space Exploration of Pareto-Optimal Architectures for Deep Learning with DVFS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Fully Synthesizable, Rail-to-Rail Dynamic Voltage Comparator for Operation down to 0.3 V.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE Frontiers in Education Conference, 2018
Energy-performance design exploration of a low-power microprogrammed deep-learning accelerator.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Display Stream Compression Encoder Architectures for Real-time 4K and 8K Video Encoding.
Proceedings of the 52nd Asilomar Conference on Signals, Systems, and Computers, 2018
2017
Design-Oriented Energy Models for Wide Voltage Scaling Down to the Minimum Energy Point.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
A Novel Framework to Estimate the Path Delay Variability On the Back of an Envelope via the Fan-Out-of-4 Metric.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
Guest Editorial Special Issue on Circuits and Systems for the Internet of Things - From Sensing to Sensemaking.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
STT-MRAM memories for IoT applications: Challenges and opportunities at circuit level and above.
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017
26.3 Reconfigurable clock networks for random skew mitigation from subthreshold to nominal voltage.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Transistor sizing strategy for simultaneous energy-delay optimization in CMOS buffers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Design-oriented models for quick estimation of path delay variability via the fan-out-of-4 metric.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Energy-quality scalable adaptive VLSI circuits and systems beyond approximate computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
A fully-synthesizable C-element based PUF featuring temperature variation compensation with native 2.8% BER, 1.02fJ/b at 0.8-1.0V in 40nm.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
EQSCALE: Energy-quality scalable feature extraction engine for Sub-mW real-time video processing with 0.55 mm<sup>2</sup> area in 40nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
Static Physically Unclonable Functions for Secure Chip Identification With 1.9-5.8% Native Bit Instability at 0.6-1 V and 15 fJ/bit in 65 nm.
IEEE J. Solid State Circuits, 2016
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
Proceedings of the VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability, 2016
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016
8.8 iRazor: 3-transistor current-based error detection and correction in an ARM Cortex-R4 processor.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
17.3 A reconfigurable dual-port memory with error detection and correction in 28nm FDSOI.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
STT-MRAM write energy minimization via area optimization under dynamic voltage Scaling.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
2015
Novel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case Study.
IEEE Trans. Very Large Scale Integr. Syst., 2015
Analysis and Characterization of Variability in Subthreshold Source-Coupled Logic Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Variations in Nanometer CMOS Flip-Flops: Part I - Impact of Process Variations on Timing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Variations in Nanometer CMOS Flip-Flops: Part II - Energy Variability and Impact of Other Sources of Variations.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
SRAM for Error-Tolerant Applications With Dynamic Energy-Quality Management in 28 nm CMOS.
IEEE J. Solid State Circuits, 2015
Proceedings of the Symposium on VLSI Circuits, 2015
Better-than-voltage scaling energy reduction in approximate SRAMs via bit dropping and bit reuse.
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
14.3 15fJ/b static physically unclonable functions for secure chip identification with <2% native bit instability and 140× Inter/Intra PUF hamming distance separation in 65nm.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
AES architectures for minimum-energy operation and silicon demonstration in 65nm with lowest energy per encryption.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Jitter analysis and measurement in subthreshold source-coupled differential ring oscillators.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Modeling the impact of dynamic voltage scaling on 1T-1J STT-RAM write energy and performance.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Comparative analysis of the robustness of master-slave flip-flops against variations.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
Proceedings of the European Conference on Circuit Theory and Design, 2015
2014
Tunnel FETs for Ultralow Voltage Digital VLSI Circuits: Part I - Device-Circuit Interaction and Evaluation at Device Level.
IEEE Trans. Very Large Scale Integr. Syst., 2014
Novel Class of Energy-Efficient Very High-Speed Conditional Push-Pull Pulsed Latches.
IEEE Trans. Very Large Scale Integr. Syst., 2014
Tunnel FETs for Ultra-Low Voltage Digital VLSI Circuits: Part II-Evaluation at Circuit Level and Design Perspectives.
IEEE Trans. Very Large Scale Integr. Syst., 2014
Effectiveness of Leakage Power Analysis Attacks on DPA-Resistant Logic Styles Under Process Variations.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Microelectron. Reliab., 2014
A 346 µm 2 VCO-Based, Reference-Free, Self-Timed Sensor Interface for Cubic-Millimeter Sensor Nodes in 28 nm CMOS.
IEEE J. Solid State Circuits, 2014
Enhancing the Static Noise Margins by Upsizing Length for Ultra-Low Voltage/Power/Energy Gates.
J. Low Power Electron., 2014
Performance and Impact of Process Variations in Tunnel-FET Ultra-Low Voltage Digital Circuits.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014
Device-circuit co-design and comparison of ultra-low voltage Tunnel-FET and CMOS digital circuits.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014
Leakage Power Analysis attacks against a bit slice implementation of the Serpent block cipher.
Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems, 2014
13.8 A 32kb SRAM for error-free and error-tolerant applications with dynamic energy-quality management in 28nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Proceedings of the 2014 IEEE Hot Chips 26 Symposium (HCS), 2014
2013
"EChO" Reconfigurable Power Management Unit for Energy Reduction in Sleep-Active Transitions.
IEEE J. Solid State Circuits, 2013
New topic session 7B: Challenges and directions for ultra-low voltage VLSI circuits and systems: CMOS and beyond.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013
Proceedings of the International Symposium on Quality Electronic Design, 2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
Buried Silicon-Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits Under Aggressive Voltage Scaling.
IEEE Trans. Very Large Scale Integr. Syst., 2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
Understanding the Basic Advantages of Bulk FinFETs for Sub- and Near-Threshold Logic Circuits From Device Measurements.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
Guest Editorial for the Special Issue on Ultra-Low-Voltage VLSI Circuits and Systems for Green Computing.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
Int. J. Circuit Theory Appl., 2012
Conditional push-pull pulsed latches with 726fJ·ps energy-delay product in 65nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 38th European Solid-State Circuit conference, 2012
Reconfigurable sleep transistor for GIDL reduction in ultra-low standby power systems.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
EChO power management unit with reconfigurable switched-capacitor converter in 65 nm CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2011
Understanding the Potential and the Limits of Germanium pMOSFETs for VLSI Circuits From Experimental Measurements.
IEEE Trans. Very Large Scale Integr. Syst., 2011
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part II - Results and Figures of Merit.
IEEE Trans. Very Large Scale Integr. Syst., 2011
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I - Methodology and Design Strategies.
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
Microelectron. J., 2011
Tapered-VTH CMOS buffer design for improved energy efficiency in deep nanometer technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Leakage Power Analysis attacks: Effectiveness on DPA resistant logic styles under process variations.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Experimental analysis of buried SiGe pMOSFETs from the perspective of aggressive voltage scaling.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Optimization and evaluation of tapered-VTH approach for energy-efficient CMOS buffers.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
2010
A General Power Model of Differential Power Analysis Attacks to Static Logic Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2010
Understanding the Effect of Process Variations on the Delay of Static and Domino Logic.
IEEE Trans. Very Large Scale Integr. Syst., 2010
Leakage-Delay Tradeoff in FinFET Logic Circuits: A Comparative Analysis With Bulk Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2010
Differential Power Analysis Attacks to Precharged Buses: A General Analysis for Symmetric-Key Cryptographic Algorithms.
IEEE Trans. Dependable Secur. Comput., 2010
Leakage Power Analysis Attacks: A Novel Class of Attacks to Nanometer Cryptographic Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
Flip-Flop Energy/Performance Versus Clock Slope and Impact on the Clock Network Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
Optimization of the wire grid size for differential routing: Analysis and impact on the power-delay-area tradeoff.
Microelectron. J., 2010
A Variability-Tolerant Feedback Technique for Throughput Maximization of Trbgs with Predefined Entropy.
J. Circuits Syst. Comput., 2010
Int. J. Circuit Theory Appl., 2010
Physical Design Aware Comparison of Flip-Flops for High-Speed Energy-Efficient VLSI Circuits.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010
Design metrics for RTL level estimation of delay variability due to intradie (random) variations.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Experimental study of leakage-delay trade-off in Germanium pMOSFETs for logic circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Clock distribution in clock domains with Dual-Edge-Triggered Flip-Flops to improve energy-efficiency.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Exploiting locality to improve leakage reduction in embedded drowsy I-caches at same area/speed.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
IEEE Trans. Circuits Syst. II Express Briefs, 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Optimization of Wire Grid Size for Differential Routing and Impact on the Power-delay-area Tradeoff.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009
Correct procedures to evaluate the effect of intradie variations on the delay variability of digital circuits.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009
Impact of clock slope on energy/delay of pulsed flip-flops and optimum clock domain design.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009
2008
IEEE Trans. Circuits Syst. II Express Briefs, 2008
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008
Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008
Improving the power-delay product in SCL circuits using source follower output stage.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Analysis and performance evaluation of area-efficient true random bit generators on FPGAs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
IEEE Trans. Circuits Syst. II Express Briefs, 2007
A Class of Maximum-Period Nonlinear Congruential Generators Derived From the Rényi Chaotic Map.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
Microelectron. J., 2007
Mixed Techniques to Protect Precharged Busses against Differential Power Analysis Attacks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
High-Speed/Low-Power Mixed Full Adder Chains: Analysis and Comparison versus Technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
A General Model of DPA Attacks to Precharged Busses in Symmetric-Key Cryptographic Algorithms.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
Very high-speed carry computation based on mixed dynamic/transmission-gate Full Adders.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
The Digital Tent Map: Performance Analysis and Optimized Design as a Low-Complexity Source of Pseudorandom Bits.
IEEE Trans. Instrum. Meas., 2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
IEEE Trans. Circuits Syst. I Regul. Pap., 2006
Techniques to Enhance the Resistance of Precharged Busses to Differential Power Analysis.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
Power Modeling of Precharged Address Bus and Application to Multi-bit DPA Attacks to DES Algorithm.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Efficient output transition time modeling in CMOS gates with ramp/exponential inputs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Modeling of Delay Variability Due to Supply Variations in Pass-Transistor and Static Full Adders.
Proceedings of the 13th IEEE International Conference on Electronics, 2006
Proceedings of the 13th IEEE International Conference on Electronics, 2006
Proceedings of the 13th IEEE International Conference on Electronics, 2006
2005
Int. J. Circuit Theory Appl., 2005
Int. J. Circuit Theory Appl., 2005
Proceedings of the Integrated Circuit and System Design, 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2004
IEEE Trans. Very Large Scale Integr. Syst., 2004
IEEE Trans. Circuits Syst. I Regul. Pap., 2004
Int. J. Circuit Theory Appl., 2004
A gate-level strategy to design Carry Select Adders.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Positive-Feedback Source-Coupled Logic: a delay model.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004
2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
2002
IEEE Trans. Very Large Scale Integr. Syst., 2002
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002
2001
IEEE Trans. Very Large Scale Integr. Syst., 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
2000
Modeling of Power Consumption of Adiabatic Gates versus Fan in and Comparison with Conventional Gates.
Proceedings of the Integrated Circuit Design, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
1999
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
1998
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998