Massimo Alioto

According to our database1, Massimo Alioto authored at least 214 papers between 1998 and 2020.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2016, "For contributions to energy-efficient VLSI circuits".

Timeline

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On csauthors.net:

Bibliography

2020
Editorial on the Opening of the New Editorial Year - The State of the IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
IEEE Trans. VLSI Syst., 2020

Energy-Quality Scalable Memory-Frugal Feature Extraction for Always-On Deep Sub-mW Distributed Vision.
IEEE Access, 2020

2019
Energy-Quality Scalable Adders Based on Nonzeroing Bit Truncation.
IEEE Trans. VLSI Syst., 2019

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
IEEE Trans. VLSI Syst., 2019

Editorial: TVLSI Keynote Papers Enriching Our Transactions With Invited Contributions.
IEEE Trans. VLSI Syst., 2019

Fully Synthesizable Low-Area Digital-to-Analog Converter With Graceful Degradation and Dynamic Power-Resolution Scaling.
IEEE Trans. on Circuits and Systems, 2019

Reconfigurable Clock Networks for Wide Voltage Scaling.
J. Solid-State Circuits, 2019

A pW-Power Hz-Range Oscillator Operating With a 0.3-1.8-V Unregulated Supply.
J. Solid-State Circuits, 2019

Token-Based Security for the Internet of Things With Dynamic Energy-Quality Tradeoff.
IEEE Internet of Things Journal, 2019

Standard Cell-Based Ultra-Compact DACs in 40-nm CMOS.
IEEE Access, 2019

Integrated Power Management and Microcontroller for Ultra-Wide Power Adaptation down to nW.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

Wake-Up Oscillators with pW Power Consumption in Dynamic Leakage Suppression Logic.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Energy-Quality Scalable Analog-to-Digital Conversion and Machine Learning Engine in a 51.9 nJ/frame Voice Activity Detector.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

An Energy Aware Variation-Tolerant Writing Termination Control for STT-based Non Volatile Flip-Flops.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Fully-Synthesizable Current-Input ADCs for Ultra-Low Area and Minimal Design Effort.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Minimum-Effort Design of Ultra-Low Power Interfaces for the Internet of Things.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

PUF-based Key Generation with Design Margin Reduction via In-Situ and PVT Sensor Fusion.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

Low-Swing Links with Dynamic Energy-Quality Trade-off for Error-Resilient Applications.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

Enabling Ubiquitous Hardware Security via Energy-Efficient Primitives and Systems : (Invited Paper).
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
A Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/STT-MTJ Circuits.
IEEE Trans. on Circuits and Systems, 2018

Time-Based Sensing for Reference-Less and Robust Read in STT-MRAM Memories.
IEEE Trans. on Circuits and Systems, 2018

Dynamic Reference Voltage Sensing Scheme for Read Margin Improvement in STT-MRAMs.
IEEE Trans. on Circuits and Systems, 2018

iRazor: Current-Based Error Detection and Correction Scheme for PVT Variation in 40-nm ARM Cortex-R4 Processor.
J. Solid-State Circuits, 2018

Fully Synthesizable PUF Featuring Hysteresis and Temperature Compensation for 3.2% Native BER and 1.02 fJ/b in 40 nm.
J. Solid-State Circuits, 2018

Dynamically Adaptable Pipeline for Energy-Efficient Microarchitectures Under Wide Voltage Scaling.
J. Solid-State Circuits, 2018

Guest Editorial Special Issue on Selected Papers from PRIME 2017 and SMACD 2017.
Integr., 2018

Energy-Quality Scalable Integrated Circuits and Systems: Continuing Energy Scaling in the Twilight of Moore's Law.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Guest Editorial Energy-Quality Scalable Circuits and Systems for Sensing and Computing: From Approximate to Communication-Inspired and Learning-Based.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Ultra-Low Power Crypto-Engine Based on Simon 32/64 for Energy- and Area-Constrained Integrated Systems.
CoRR, 2018

The Internet of Things on Its Edge: Trends Toward Its Tipping Point.
IEEE Consumer Electronics Magazine, 2018

A Sub-Leakage PW-Power HZ-Range Relaxation Oscillator Operating with 0.3V-1.8V Unregulated Supply.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 595pW 14pJ/Cycle microcontroller with dual-mode standard cells and self-startup for battery-indifferent distributed sensing.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Design-Space Exploration of Pareto-Optimal Architectures for Deep Learning with DVFS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Novel Time-Based Sensing Scheme for STT-MRAMs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Fully Synthesizable, Rail-to-Rail Dynamic Voltage Comparator for Operation down to 0.3 V.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Project-Based Learning in Digital Fundamentals Course Using FPGAs.
Proceedings of the IEEE Frontiers in Education Conference, 2018

Energy-performance design exploration of a low-power microprogrammed deep-learning accelerator.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Display Stream Compression Encoder Architectures for Real-time 4K and 8K Video Encoding.
Proceedings of the 52nd Asilomar Conference on Signals, Systems, and Computers, 2018

2017
Editorial.
IEEE Trans. VLSI Syst., 2017

Editorial.
IEEE Trans. VLSI Syst., 2017

Design-Oriented Energy Models for Wide Voltage Scaling Down to the Minimum Energy Point.
IEEE Trans. on Circuits and Systems, 2017

A Novel Framework to Estimate the Path Delay Variability On the Back of an Envelope via the Fan-Out-of-4 Metric.
IEEE Trans. on Circuits and Systems, 2017

Guest Editorial Special Issue on Circuits and Systems for the Internet of Things - From Sensing to Sensemaking.
IEEE Trans. on Circuits and Systems, 2017

STT-MRAM memories for IoT applications: Challenges and opportunities at circuit level and above.
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

26.3 Reconfigurable clock networks for random skew mitigation from subthreshold to nominal voltage.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

A variation-aware simulation framework for hybrid CMOS/spintronic circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Transistor sizing strategy for simultaneous energy-delay optimization in CMOS buffers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Power-precision scalable latch memories.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Design-oriented models for quick estimation of path delay variability via the fan-out-of-4 metric.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Energy-quality scalable adaptive VLSI circuits and systems beyond approximate computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

A fully-synthesizable C-element based PUF featuring temperature variation compensation with native 2.8% BER, 1.02fJ/b at 0.8-1.0V in 40nm.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

EQSCALE: Energy-quality scalable feature extraction engine for Sub-mW real-time video processing with 0.55 mm2 area in 40nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016
Approximate SRAMs With Dynamic Energy-Quality Management.
IEEE Trans. VLSI Syst., 2016

Editorial First TVLSI Best AE and Reviewer Awards.
IEEE Trans. VLSI Syst., 2016

Novel Boosted-Voltage Sensing Scheme for Variation-Resilient STT-MRAM Read.
IEEE Trans. on Circuits and Systems, 2016

Static Physically Unclonable Functions for Secure Chip Identification With 1.9-5.8% Native Bit Instability at 0.6-1 V and 15 fJ/bit in 65 nm.
J. Solid-State Circuits, 2016

Voltage Scaled STT-MRAMs Towards Minimum-Energy Write Access.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Beyond Ideal DVFS Through Ultra-Fine Grain Vdd-Hopping.
Proceedings of the VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability, 2016

Ultra-Fine Grain Vdd-Hopping for energy-efficient Multi-Processor SoCs.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

8.8 iRazor: 3-transistor current-based error detection and correction in an ARM Cortex-R4 processor.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

17.3 A reconfigurable dual-port memory with error detection and correction in 28nm FDSOI.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

STT-MRAM write energy minimization via area optimization under dynamic voltage Scaling.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Boosted sensing for enhanced read stability in STT-MRAMs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Ultra-low voltage standard cell libraries: Design strategies and a case study.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

A closed-form energy model for VLSI circuits under wide voltage scaling.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015
Novel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case Study.
IEEE Trans. VLSI Syst., 2015

Analysis and Characterization of Variability in Subthreshold Source-Coupled Logic Circuits.
IEEE Trans. on Circuits and Systems, 2015

Variations in Nanometer CMOS Flip-Flops: Part I - Impact of Process Variations on Timing.
IEEE Trans. on Circuits and Systems, 2015

Variations in Nanometer CMOS Flip-Flops: Part II - Energy Variability and Impact of Other Sources of Variations.
IEEE Trans. on Circuits and Systems, 2015

SRAM for Error-Tolerant Applications With Dynamic Energy-Quality Management in 28 nm CMOS.
J. Solid-State Circuits, 2015

A reconfigurable sense amplifier with 3X offset reduction in 28nm FDSOI CMOS.
Proceedings of the Symposium on VLSI Circuits, 2015

Better-than-voltage scaling energy reduction in approximate SRAMs via bit dropping and bit reuse.
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015

Variability budgetin pulsed flip-flops.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

14.3 15fJ/b static physically unclonable functions for secure chip identification with <2% native bit instability and 140× Inter/Intra PUF hamming distance separation in 65nm.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

AES architectures for minimum-energy operation and silicon demonstration in 65nm with lowest energy per encryption.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Jitter analysis and measurement in subthreshold source-coupled differential ring oscillators.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Modeling the impact of dynamic voltage scaling on 1T-1J STT-RAM write energy and performance.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Comparative analysis of the robustness of master-slave flip-flops against variations.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

PVT variations in differential flip-flops: A comparative analysis.
Proceedings of the European Conference on Circuit Theory and Design, 2015

2014
Tunnel FETs for Ultralow Voltage Digital VLSI Circuits: Part I - Device-Circuit Interaction and Evaluation at Device Level.
IEEE Trans. VLSI Syst., 2014

Novel Class of Energy-Efficient Very High-Speed Conditional Push-Pull Pulsed Latches.
IEEE Trans. VLSI Syst., 2014

Tunnel FETs for Ultra-Low Voltage Digital VLSI Circuits: Part II-Evaluation at Circuit Level and Design Perspectives.
IEEE Trans. VLSI Syst., 2014

Effectiveness of Leakage Power Analysis Attacks on DPA-Resistant Logic Styles Under Process Variations.
IEEE Trans. on Circuits and Systems, 2014

Comparative soft error evaluation of layout cells in FinFET technology.
Microelectron. Reliab., 2014

A 346 µm 2 VCO-Based, Reference-Free, Self-Timed Sensor Interface for Cubic-Millimeter Sensor Nodes in 28 nm CMOS.
J. Solid-State Circuits, 2014

Enhancing the Static Noise Margins by Upsizing Length for Ultra-Low Voltage/Power/Energy Gates.
J. Low Power Electronics, 2014

Performance and Impact of Process Variations in Tunnel-FET Ultra-Low Voltage Digital Circuits.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

Device-circuit co-design and comparison of ultra-low voltage Tunnel-FET and CMOS digital circuits.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

Leakage Power Analysis attacks against a bit slice implementation of the Serpent block cipher.
Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems, 2014

Ultra-low power design approaches for IoT.
Proceedings of the 2014 IEEE Hot Chips 26 Symposium (HCS), 2014

2013
"EChO" Reconfigurable Power Management Unit for Energy Reduction in Sleep-Active Transitions.
J. Solid-State Circuits, 2013

New topic session 7B: Challenges and directions for ultra-low voltage VLSI circuits and systems: CMOS and beyond.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Enabling sizing for enhancing the static noise margins.
Proceedings of the International Symposium on Quality Electronic Design, 2013

45pW ESD clamp circuit for ultra-low power applications.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
Buried Silicon-Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits Under Aggressive Voltage Scaling.
IEEE Trans. VLSI Syst., 2012

Mixed FBB/RBB: A Novel Low-Leakage Technique for FinFET Forced Stacks.
IEEE Trans. VLSI Syst., 2012

A Simple Circuit Approach to Reduce Delay Variations in Domino Logic Gates.
IEEE Trans. on Circuits and Systems, 2012

Understanding the Basic Advantages of Bulk FinFETs for Sub- and Near-Threshold Logic Circuits From Device Measurements.
IEEE Trans. on Circuits and Systems, 2012

Guest Editorial for the Special Issue on Ultra-Low-Voltage VLSI Circuits and Systems for Green Computing.
IEEE Trans. on Circuits and Systems, 2012

Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial.
IEEE Trans. on Circuits and Systems, 2012

From energy-delay metrics to constraints on the design of digital circuits.
I. J. Circuit Theory and Applications, 2012

Conditional push-pull pulsed latches with 726fJ·ps energy-delay product in 65nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A simple keeper topology to reduce delay variations in nanometer domino logic.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Active RFID: Perpetual wireless communications platform for sensors.
Proceedings of the 38th European Solid-State Circuit conference, 2012

Reconfigurable sleep transistor for GIDL reduction in ultra-low standby power systems.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

EChO power management unit with reconfigurable switched-capacitor converter in 65 nm CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
Understanding the Potential and the Limits of Germanium pMOSFETs for VLSI Circuits From Experimental Measurements.
IEEE Trans. VLSI Syst., 2011

Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part II - Results and Figures of Merit.
IEEE Trans. VLSI Syst., 2011

Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I - Methodology and Design Strategies.
IEEE Trans. VLSI Syst., 2011

Comparative Evaluation of Layout Density in 3T, 4T, and MT FinFET Standard Cells.
IEEE Trans. VLSI Syst., 2011

Tapered-Vth Approach for Energy-Efficient CMOS Buffers.
IEEE Trans. on Circuits and Systems, 2011

Modeling strategies of the input admittance of RC interconnects for VLSI CAD tools.
Microelectron. J., 2011

Optimized design of parallel carry-select adders.
Integr., 2011

Tapered-VTH CMOS buffer design for improved energy efficiency in deep nanometer technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Leakage Power Analysis attacks: Effectiveness on DPA resistant logic styles under process variations.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Experimental analysis of buried SiGe pMOSFETs from the perspective of aggressive voltage scaling.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A novel back-biasing low-leakage technique for FinFET forced stacks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

DET FF topologies: A detailed investigation in the energy-delay-area domain.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Optimization and evaluation of tapered-VTH approach for energy-efficient CMOS buffers.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

Impact of NMOS/PMOS imbalance in Ultra-Low Voltage CMOS standard cells.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010
A General Power Model of Differential Power Analysis Attacks to Static Logic Circuits.
IEEE Trans. VLSI Syst., 2010

Understanding the Effect of Process Variations on the Delay of Static and Domino Logic.
IEEE Trans. VLSI Syst., 2010

Leakage-Delay Tradeoff in FinFET Logic Circuits: A Comparative Analysis With Bulk Technology.
IEEE Trans. VLSI Syst., 2010

Differential Power Analysis Attacks to Precharged Buses: A General Analysis for Symmetric-Key Cryptographic Algorithms.
IEEE Trans. Dependable Sec. Comput., 2010

Leakage Power Analysis Attacks: A Novel Class of Attacks to Nanometer Cryptographic Circuits.
IEEE Trans. on Circuits and Systems, 2010

General Strategies to Design Nanometer Flip-Flops in the Energy-Delay Space.
IEEE Trans. on Circuits and Systems, 2010

Flip-Flop Energy/Performance Versus Clock Slope and Impact on the Clock Network Design.
IEEE Trans. on Circuits and Systems, 2010

Understanding DC Behavior of Subthreshold CMOS Logic Through Closed-Form Analysis.
IEEE Trans. on Circuits and Systems, 2010

Optimization of the wire grid size for differential routing: Analysis and impact on the power-delay-area tradeoff.
Microelectron. J., 2010

A Variability-Tolerant Feedback Technique for Throughput Maximization of Trbgs with Predefined Entropy.
Journal of Circuits, Systems, and Computers, 2010

Simple and accurate modeling of the output transition time in nanometer CMOS gates.
I. J. Circuit Theory and Applications, 2010

Physical Design Aware Comparison of Flip-Flops for High-Speed Energy-Efficient VLSI Circuits.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010

Design metrics for RTL level estimation of delay variability due to intradie (random) variations.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Experimental study of leakage-delay trade-off in Germanium pMOSFETs for logic circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Clock distribution in clock domains with Dual-Edge-Triggered Flip-Flops to improve energy-efficiency.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Exploiting locality to improve leakage reduction in embedded drowsy I-caches at same area/speed.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Analysis of layout density in FinFET standard cells and impact of fin technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Closed-form analysis of DC noise immunity in subthreshold CMOS logic circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Analysis and Modeling of Energy Consumption in RLC Tree Circuits.
IEEE Trans. VLSI Syst., 2009

Improving Power-Delay Performance of Ultra-Low-Power Subthreshold SCL Circuits.
IEEE Trans. on Circuits and Systems, 2009

Analysis and Design of Ultra-low Power Subthreshold MCML Gates.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Metrics and Design Considerations on the Energy-delay Tradeoff of Digital Circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Optimization of Wire Grid Size for Differential Routing and Impact on the Power-delay-area Tradeoff.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Understanding Loading Effects of RC Uniform Interconnects.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Analysis of the impact of random process variations in CMOS tapered buffers.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

Leakage Power Analysis attacks: Theoretical analysis and impact of variations.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

Optimum clock slope for flip-flops within a clock domain: Analysis and a case study.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008
Power-Aware Design of Nanometer MCML Tapered Buffers.
IEEE Trans. on Circuits and Systems, 2008

Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

Design and Evaluation of Mixed 3T-4T FinFET Stacks for Leakage Reduction.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

Improving the power-delay product in SCL circuits using source follower output stage.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A general model for differential power analysis attacks to static logic circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Explicit energy evaluation in RLC tree circuits with ramp inputs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Power-delay optimization in MCML tapered buffers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Analysis and performance evaluation of area-efficient true random bit generators on FPGAs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Energy evaluation in RLC tree circuits with exponential input.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Analysis of the impact of process variations on static logic circuits versus fan-in.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007
Power-Delay-Area-Noise Margin Tradeoffs in Positive-Feedback MOS Current-Mode Logic.
IEEE Trans. on Circuits and Systems, 2007

Interconnect-Aware Design of Fast Large Fan-In CMOS Multiplexers.
IEEE Trans. on Circuits and Systems, 2007

A Class of Maximum-Period Nonlinear Congruential Generators Derived From the Rényi Chaotic Map.
IEEE Trans. on Circuits and Systems, 2007

Mixed Full Adder topologies for high-performance low-power arithmetic circuits.
Microelectron. J., 2007

Mixed Techniques to Protect Precharged Busses against Differential Power Analysis Attacks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Delay Variability Due to Supply Variations in Transmission-Gate Full Adders.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Design of Fast Large Fan-In CMOS Multiplexers Accounting for Interconnects.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

High-Speed/Low-Power Mixed Full Adder Chains: Analysis and Comparison versus Technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Maximum-Period PRNGs Derived From A Piecewise Linear One-Dimensional Map.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Efficient and Accurate Models of Output Transition Time in CMOS Logic.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

A Simple and Accurate Model of Input capacitance for Power Estimation in CMOS logic.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006
Energy Consumption in RC Tree Circuits.
IEEE Trans. VLSI Syst., 2006

Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison.
IEEE Trans. VLSI Syst., 2006

The Digital Tent Map: Performance Analysis and Optimized Design as a Low-Complexity Source of Pseudorandom Bits.
IEEE Trans. Instrumentation and Measurement, 2006

Exploiting Hysteresys in MCML Circuits.
IEEE Trans. on Circuits and Systems, 2006

Design strategies of cascaded CML gates.
IEEE Trans. on Circuits and Systems, 2006

Design of High-Speed Power-Efficient MOS Current-Mode Logic Frequency Dividers.
IEEE Trans. on Circuits and Systems, 2006

Low-hardware complexity PRBGs based on a piecewise-linear chaotic map.
IEEE Trans. on Circuits and Systems, 2006

A feedback strategy to improve the entropy of a chaos-based random bit generator.
IEEE Trans. on Circuits and Systems, 2006

Techniques to Enhance the Resistance of Precharged Busses to Differential Power Analysis.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Power Modeling of Precharged Address Bus and Application to Multi-bit DPA Attacks to DES Algorithm.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Analysis and design of MCML gates with hysteresis.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Efficient output transition time modeling in CMOS gates with ramp/exponential inputs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Nanometer MCML gates: models and design considerations.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Delay uncertainty due to supply variations in static and dynamic full adders.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A technique to design high entropy chaos-based true random bit generators.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Modeling of Delay Variability Due to Supply Variations in Pass-Transistor and Static Full Adders.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

A Design Methodology for High-Speed Low-Power MCML Frequency Dividers.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Efficient Post-Processing Module for a Chaos-based Random Bit Generator.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
Modelling and design considerations on CML gates under high-current effects.
I. J. Circuit Theory and Applications, 2005

Power-delay optimization of D-latch/MUX source coupled logic gates.
I. J. Circuit Theory and Applications, 2005

Energy Consumption in RC Tree Circuits with Exponential Inputs: An Analytical Model.
Proceedings of the Integrated Circuit and System Design, 2005

Design techniques for low-power cascaded CML gates.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

An approach to the design of PFSCL gates.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Long period pseudo random bit generators derived from a discretized chaotic map.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Evaluation of energy consumption in RC ladder circuits driven by a ramp input.
IEEE Trans. VLSI Syst., 2004

Modeling and evaluation of positive-feedback source-coupled logic.
IEEE Trans. on Circuits and Systems, 2004

An efficient implementation of PRNGs based on the digital sawtooth map.
I. J. Circuit Theory and Applications, 2004

A gate-level strategy to design Carry Select Adders.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Positive-Feedback Source-Coupled Logic: a delay model.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Hardware-efficient PRBGs based on 1-D piecewise linear chaotic maps.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

2003
Performance evaluation of the low-voltage CML D-latch topology.
Integr., 2003

Design of MUX, XOR and D-latch SCL gates.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Analysis and design of digital PRNGS based on the discretized sawtooth map.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

2002
Analysis and comparison on full adder block in submicron technology.
IEEE Trans. VLSI Syst., 2002

Modelling of source-coupled logic gates.
I. J. Circuit Theory and Applications, 2002

An Approach to Energy Consumption Modeling in RC Ladder Circuits.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Modeling Propagation Delay of MUX, XOR, and D-Latch Source-Coupled Logic Gates.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Power-delay trade-offs in SCL gates.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
Power estimation in adiabatic circuits: a simple and accurate model.
IEEE Trans. VLSI Syst., 2001

CML ring oscillators: oscillation frequency.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
Modeling of Power Consumption of Adiabatic Gates versus Fan in and Comparison with Conventional Gates.
Proceedings of the Integrated Circuit Design, 2000

High-speed bipolar MUX modeling and design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Evaluation of power consumption in adiabatic circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
Highly accurate and simple models for CML and ECL gates.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

1998
Novel Simple Models Of Cml Propagation Delay.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998


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