Luca Gallo

According to our database, Luca Gallo authored at least 17 papers between 2013 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

MPXGAT: An Attention based Deep Learning Model for Multiplex Graphs Embedding.

Marco Bongiovanni, Luca Gallo, Roberto Grasso, Alfredo Pulvirenti

CoRR, 2024

2023

Hypergraphx: a library for higher-order network analysis.

Quintino Francesco Lotito, Martina Contisciani, Caterina De Bacco, Leonardo Di Gaetano, Luca Gallo, Alberto Montresor, Federico Musciotto, Nicolò Ruggeri, Federico Battiston

J. Complex Networks, April, 2023

Complex contagion in social systems with distrust.

Jean-François de Kemmeter, Luca Gallo, Fabrizio Boncoraglio, Vito Latora, Timoteo Carletti

CoRR, 2023

Higher-order correlations reveal complex memory in temporal hypergraphs.

Luca Gallo, Lucas Lacasa, Vito Latora, Federico Battiston

CoRR, 2023

2022

MultiSAGE: a multiplex embedding algorithm for inter-layer link prediction.

Luca Gallo, Vito Latora, Alfredo Pulvirenti

CoRR, 2022

2020

Assessing the robustness of decentralized gathering: a multi-agent approach on micro-biological systems.

Daniele Proverbio, Luca Gallo, Barbara Passalacqua, Marco Destefanis, Marco Maggiora, Jacopo Pellegrino

Swarm Intell., 2020

2015

Methodologies for automated synthesis of memory and interconnect subsystems in parallel architectures.

Luca Gallo

PhD thesis, 2015

Exploiting Concurrency for the Automated Synthesis of MPSoC Interconnects.

Alessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo

ACM Trans. Embed. Comput. Syst., 2015

Interplay of loop unrolling and multidimensional memory partitioning in HLS.

Alessandro Cilardo, Luca Gallo

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Improving Multibank Memory Access Parallelism with Lattice-Based Partitioning.

Alessandro Cilardo, Luca Gallo

ACM Trans. Archit. Code Optim., 2014

Automated design space exploration for FPGA-based heterogeneous interconnects.

Alessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo, Nicola Mazzocca

Des. Autom. Embed. Syst., 2014

Area implications of memory partitioning for high-level synthesis on FPGAs.

Luca Gallo, Alessandro Cilardo, David B. Thomas, Samuel Bayliss, George A. Constantinides

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Generating On-Chip Heterogeneous Systems from High-Level Parallel Code.

Alessandro Cilardo, Luca Gallo

Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Joint communication scheduling and interconnect synthesis for FPGA-based many-core systems.

Alessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Design space exploration for high-level synthesis of multi-threaded applications.

Alessandro Cilardo, Luca Gallo, Nicola Mazzocca

J. Syst. Archit., 2013

Automated synthesis of FPGA-based heterogeneous interconnect topologies.

Alessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Efficient and scalable OpenMP-based system-level design.

Alessandro Cilardo, Luca Gallo, Antonino Mazzeo, Nicola Mazzocca

Proceedings of the Design, Automation and Test in Europe, 2013