Alessandro Cilardo

Orcid: 0000-0002-1685-8736

According to our database1, Alessandro Cilardo authored at least 92 papers between 2003 and 2022.

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Bibliography

2022
Virtualization Over Multiprocessor Systems-on-Chip: An Enabling Paradigm for the Industrial Internet of Things.
Computer, 2022

A Proposal for FPGA-Accelerated Deep Learning Ensembles in MPSoC Platforms Applied to Malware Detection.
Proceedings of the Quality of Information and Communications Technology, 2022

A Pluggable Vector Unit for RISC-V Vector Extension.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
Evaluation of HPC Acceleration and Interconnect Technologies for High-Throughput Data Acquisition.
Sensors, 2021

Predictive Reliability and Fault Management in Exascale Systems: State of the Art and Perspectives.
ACM Comput. Surv., 2021

Virtualization over Multiprocessor System-on-Chip: an Enabling Paradigm for Industrial IoT.
CoRR, 2021

SPHERE: A Multi-SoC Architecture for Next-Generation Cyber-Physical Systems Based on Heterogeneous Platforms.
IEEE Access, 2021

Memory Encryption Support for an FPGA-based RISC-V Implementation.
Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021

FPGA-based real-time monitoring support for CAN applications.
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021


2020
The RECIPE approach to challenges in deeply heterogeneous high performance systems.
Microprocess. Microsystems, 2020

Designing a SHA-256 processor for blockchain-based IoT applications.
Internet Things, 2020

Hardware support for thread synchronisation in an experimental manycore system.
Int. J. Grid Util. Comput., 2020

SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey.
IEEE Access, 2020

2019
A Flexible Framework for Exploring, Evaluating, and Comparing SHA-2 Designs.
IEEE Access, 2019

Challenges in Deeply Heterogeneous High Performance Systems.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

Lightweight hardware support for selective coherence in heterogeneous manycore accelerators.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

A Configurable Implementation of the SHA-256 Hash Function.
Proceedings of the Advances on P2P, Parallel, Grid, Cloud and Internet Computing, 2019

2018
Lattice-Based Turn Model for Adaptive Routing.
IEEE Trans. Parallel Distributed Syst., 2018

An IP Core Remote Anonymous Activation Protocol.
IEEE Trans. Emerg. Top. Comput., 2018

PowerTap: All-digital power meter modeling for run-time power monitoring.
Microprocess. Microsystems, 2018

Exploring manycore architectures for next-generation HPC systems through the MANGO approach.
Microprocess. Microsystems, 2018

Reducing Power Consumption of Lasers in Photonic NoCs through Application-Specific Mapping.
ACM J. Emerg. Technol. Comput. Syst., 2018

HtComp: bringing reconfigurable hardware to future high-performance applications.
Int. J. High Perform. Comput. Netw., 2018

An abstraction layer enabling pervasive hardware-reconfigurable systems.
Int. J. Embed. Syst., 2018

Reliable power and time-constraints-aware predictive management of heterogeneous exascale systems.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

Improving Deep Learning with a customizable GPU-like FPGA-based accelerator.
Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018

Understanding turn models for adaptive routing: The modular approach.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
H<sup>2</sup>ONoC: A Hybrid Optical-Electronic NoC Based on Hybrid Topology.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Path Setup for Hybrid NoC Architectures Exploiting Flooding and Standby.
IEEE Trans. Parallel Distributed Syst., 2017

Verification of FPGA-augmented trusted computing mechanisms based on Applied Pi Calculus.
IACR Cryptol. ePrint Arch., 2017

Energy Analysis of a 4D Variational Data Assimilation Algorithm and Evaluation on ARM-Based HPC Systems.
Proceedings of the Parallel Processing and Applied Mathematics, 2017

Deeply Heterogeneous Many-Accelerator Infrastructure for HPC Architecture Exploration.
Proceedings of the Parallel Computing is Everywhere, 2017

A Proposal for the Secure Activation and Licensing of FPGA IP Cores.
Proceedings of the First Italian Conference on Cybersecurity (ITASEC17), 2017


NoC-Based Thread Synchronization in a Custom Manycore System.
Proceedings of the Advances on P2P, 2017

2016
Crosstalk-Aware Automated Mapping for Optical Networks-on-Chip.
ACM Trans. Embed. Comput. Syst., 2016

Minimizing power loss in optical networks-on-chip through application-specific mapping.
Microprocess. Microsystems, 2016

Design automation for application-specific on-chip interconnects: A survey.
Integr., 2016

PhoNoCMap: An application mapping tool for photonic networks-on-chip.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Enabling HPC for QoS-sensitive applications: The MANGO approach.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Securing the cloud with reconfigurable computing: An FPGA accelerator for homomorphic encryption.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Partial FPGA bitstream encryption enabling hardware DRM in mobile environments.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

A Configurable Shared Scratchpad Memory for GPU-like Processors.
Proceedings of the Advances on P2P, 2016

2015
New Techniques and Tools for Application-Dependent Testing of FPGA-Based Components.
IEEE Trans. Ind. Informatics, 2015

Exploiting Concurrency for the Automated Synthesis of MPSoC Interconnects.
ACM Trans. Embed. Comput. Syst., 2015

Crosstalk-Aware Mapping for Tile-Based Optical Network-on-Chip.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

Customizable Heterogeneous Acceleration for Tomorrow's High-Performance Computing.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

On the Design of a Path-Setup Architecture for Exploiting Hybrid Photonic-Electronic NoCs.
Proceedings of the 2015 Workshop on Exploiting Silicon Photonics for Energy-Efficient High Performance Computing, 2015

Scheduling-aware interconnect synthesis for FPGA-based Multi-Processor Systems-on-Chip.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Variable-latency signed addition on FPGAs.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Interplay of loop unrolling and multidimensional memory partitioning in HLS.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

The MANGO FET-HPC Project: An Overview.
Proceedings of the 18th IEEE International Conference on Computational Science and Engineering, 2015

The HtComp Research Project: An Overview.
Proceedings of the 10th International Conference on P2P, 2015

2014
High Speed Speculative Multipliers Based on Speculative Carry-Save Tree.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Improving Multibank Memory Access Parallelism with Lattice-Based Partitioning.
ACM Trans. Archit. Code Optim., 2014

ASP-based optimized mapping in a simulink-to-MPSoC design flow.
J. Syst. Archit., 2014

Secure distribution infrastructure for hardware digital contents.
IET Comput. Digit. Tech., 2014

Automated design space exploration for FPGA-based heterogeneous interconnects.
Des. Autom. Embed. Syst., 2014

Area implications of memory partitioning for high-level synthesis on FPGAs.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Generating On-Chip Heterogeneous Systems from High-Level Parallel Code.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Joint communication scheduling and interconnect synthesis for FPGA-based many-core systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Exploiting Vulnerabilities in Cryptographic Hash Functions Based on Reconfigurable Hardware.
IEEE Trans. Inf. Forensics Secur., 2013

Fast Parallel GF(2^m) Polynomial Multiplication for All Degrees.
IEEE Trans. Computers, 2013

Design space exploration for high-level synthesis of multi-threaded applications.
J. Syst. Archit., 2013

Exploring a New Dimension in Code Mobility for Ubiquitous Embedded Systems.
Proceedings of the 2013 IEEE 10th International Conference on Ubiquitous Intelligence and Computing and 2013 IEEE 10th International Conference on Autonomic and Trusted Computing, 2013

TrustedSIM: Towards Unified Mobile Security.
Proceedings of the 2013 IEEE 10th International Conference on Ubiquitous Intelligence and Computing and 2013 IEEE 10th International Conference on Autonomic and Trusted Computing, 2013

Heterogeneous Computing vs. Big Data: The Case of Cryptanalytical Applications.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2013

Automated synthesis of FPGA-based heterogeneous interconnect topologies.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Efficient and scalable OpenMP-based system-level design.
Proceedings of the Design, Automation and Test in Europe, 2013

2011
Exploring the Potential of Threshold Logic for Cryptography-Related Operations.
IEEE Trans. Computers, 2011

Revisiting Application-Dependent Test for FPGA Devices.
Proceedings of the 16th European Test Symposium, 2011

The potential of reconfigurable hardware for HPC cryptanalysis of SHA-1.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
A CellBE-based HPC Application for the Analysis of Vulnerabilities in Cryptographic Hash Functions.
Proceedings of the 12th IEEE International Conference on High Performance Computing and Communications, 2010

Early Prediction of Hardware Complexity in HLL-to-HDL Translation.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

2009
Efficient Bit-Parallel GF(2^m) Multiplier for a Large Class of Irreducible Pentanomials.
IEEE Trans. Computers, 2009

A new speculative addition architecture suitable for two's complement operations.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Time Efficient Dual-Field Unit for Cryptography-Related Processing.
Proceedings of the VLSI-SoC: Design Methodologies for SoC and SiP, 2008

Virtual Scan Chains for Online Testing of FPGA-based Embedded Systems.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007
Design and implementation of a high performance architecture for providing digital time stamping services to mobile devices.
Comput. Syst. Sci. Eng., 2007

Performance Evaluation of Security Services: An Experimental Approach.
Proceedings of the 15th Euromicro International Conference on Parallel, 2007

Combining Programmable Hardware and Web Services Technologies for Delivering High-Performance and Interoperable Security.
Proceedings of the 15th Euromicro International Conference on Parallel, 2007

Adaptable Parsing of Real-Time Data Streams.
Proceedings of the 15th Euromicro International Conference on Parallel, 2007

2006
Elliptic Curve Cryptography Engineering.
Proc. IEEE, 2006

2005
An FPGA-based Key-Store for Improving the Dependability of Security Services.
Proceedings of the 10th IEEE International Workshop on Object-Oriented Real-Time Dependable Systems (WORDS 2005), 2005

Reconfigurable systems self-healing using mobile hardware agents.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

High-Performance and Interoperable Security Services for Mobile Environments.
Proceedings of the High Performance Computing and Communications, 2005

A Novel Unified Architecture for Public-Key Cryptography.
Proceedings of the 2005 Design, 2005

2004
Exploring the design-space for FPGA-based implementation of RSA.
Microprocess. Microsystems, 2004

A Web Services Based Architecture for Digital Time Stamping.
J. Web Eng., 2004

Carry-Save Montgomery Modular Exponentiation on Reconfigurable Hardware.
Proceedings of the 2004 Design, 2004

2003
Using Web Services Technology for Inter-enterprise Integration of Digital Time Stamping.
Proceedings of the On The Move to Meaningful Internet Systems 2003: OTM 2003 Workshops, 2003


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