Samuel Bayliss

Affiliations:
  • Imperial College London, UK


According to our database1, Samuel Bayliss authored at least 19 papers between 2006 and 2020.

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Bibliography

2020
Vyasa: A High-Performance Vectorizing Compiler for Tensor Convolutions on the Xilinx AI Engine.
Proceedings of the 2020 IEEE High Performance Extreme Computing Conference, 2020

2018
Polyhedral-Based Dynamic Loop Pipelining for High-Level Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2017
Run fast when you can: Loop pipelining with uncertain and non-uniform memory dependencies.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017

2016
Separation Logic for High-Level Synthesis.
ACM Trans. Reconfigurable Technol. Syst., 2016

Survey of domain-specific languages for FPGA computing.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

2015
MATCHUP: Memory Abstractions for Heap Manipulating Programs.
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Offline Synthesis of Online Dependence Testing: Parametric Loop Pipelining for HLS.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

2014
Area implications of memory partitioning for high-level synthesis on FPGAs.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Separation Logic-Assisted Code Transformations for Efficient High-Level Synthesis.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Compiling Higher Order Functional Programs to Composable Digital Hardware.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Datapath Synthesis for Overclocking: Online Arithmetic for Latency-Accuracy Trade-offs.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

GPU vs FPGA: A Comparative Analysis for Non-standard Precision.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2013
High-level synthesis of dynamic data structures: A case study using Vivado HLS.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

SOAP: Structural optimization of arithmetic expressions for high-level synthesis.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

FPGA-based K-means clustering using tree-based data structures.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012
Analytical synthesis of bandwidth-efficient SDRAM address generators.
Microprocess. Microsystems, 2012

Optimizing SDRAM bandwidth for custom FPGA loop accelerators.
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

2011
Application Specific Memory Access, Reuse and Reordering for SDRAM.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

2006
An FPGA implementation of the simplex algorithm.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006


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