Luis Ángel García-Astudillo

According to our database, Luis Ángel García-Astudillo authored at least 4 papers between 2020 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

Error Mitigation Using Optimized Redundancy for Composite Algorithms in FPGAs.

Luis Ángel García-Astudillo, Almudena Lindoso, Luis Entrena

IEEE Trans. Aerosp. Electron. Syst., 2024

2023

Formal Verification of Fault-Tolerant Hardware Designs.

Luis Entrena, Antonio J. Sanchez-Clemente, Luis Ángel García-Astudillo, Marta Portela-García, Mario García-Valderas, Almudena Lindoso, Roberto Sarmiento

IEEE Access, 2023

2022

Reduced Resolution Redundancy: A Novel Approximate Error Mitigation Technique.

Luis Ángel García-Astudillo, Luis Entrena, Almudena Lindoso, Honorio Martín

IEEE Access, 2022

2020

Evaluation of a Reduced Precision Redundancy FFT Design.

Luis Ángel García-Astudillo, Almudena Lindoso, Marta Portela, Luis Entrena

Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020