Vicent Canals

Orcid: 0000-0002-8394-4159

According to our database1, Vicent Canals authored at least 46 papers between 2004 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2023
Fully Parallel Stochastic Computing Hardware Implementation of Convolutional Neural Networks for Edge Computing Applications.
IEEE Trans. Neural Networks Learn. Syst., December, 2023

Corrections to "Digital implementation of Radial Basis Function Neural Networks Based on Stochastic Computing".
IEEE J. Emerg. Sel. Topics Circuits Syst., September, 2023

Hardware-Optimized Reservoir Computing System for Edge Intelligence Applications.
Cogn. Comput., September, 2023

Highly Optimized Hardware Morphological Neural Network Through Stochastic Computing and Tropical Pruning.
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023

Digital Implementation of Radial Basis Function Neural Networks Based on Stochastic Computing.
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023

Approximate arithmetic aware training for stochastic computing neural networks.
Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023

2022
Hardware Implementation of Stochastic Computing-based Morphological Neural Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
Stochastic Computing co-processing elements for Evolving Autonomous Data Partitioning.
Proceedings of the XXXVI Conference on Design of Circuits and Integrated Systems, 2021

Exploiting Correlation in Stochastic Computing based Deep Neural Networks.
Proceedings of the XXXVI Conference on Design of Circuits and Integrated Systems, 2021

2020
Efficient parallel implementation of reservoir computing systems.
Neural Comput. Appl., 2020

Fully-parallel Convolutional Neural Network Hardware.
CoRR, 2020

Stochastic-based Neural Network hardware acceleration for an efficient ligand-based virtual screening.
CoRR, 2020

SoC Kohonen Maps Based on Stochastic Computing.
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020

FPGA Implementation of Random Vector Functional Link Networks based on Elementary Cellular Automata.
Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020

2019
Self-Organizing Maps hybrid Implementation Based on Stochastic Computing.
Proceedings of the XXXIV Conference on Design of Circuits and Integrated Systems, 2019

2018
A Stochastic Spiking Neural Network for Virtual Screening.
IEEE Trans. Neural Networks Learn. Syst., 2018

Reservoir Computing Hardware for Time Series Forecasting.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

Cyclic Reservoir Computing with FPGA Devices for Efficient Channel Equalization.
Proceedings of the Artificial Intelligence and Soft Computing, 2018

2017
Noise tolerant probabilistic logic for statistical pattern recognition applications.
Integr. Comput. Aided Eng., 2017

2016
A New Stochastic Computing Methodology for Efficient Neural Network Implementation.
IEEE Trans. Neural Networks Learn. Syst., 2016

High-Density Liquid-State Machine Circuitry for Time-Series Forecasting.
Int. J. Neural Syst., 2016

FPGA-Based Stochastic Echo State Networks for Time-Series Forecasting.
Comput. Intell. Neurosci., 2016

Stochastic hardware implementation of Liquid State Machines.
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016

2015
Digital Implementation of a Single Dynamical Node Reservoir Computer.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

An unconventional computing technique for ultra-fast and ultra-low power data mining.
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015

Short-Term Spanish Aggregated Solar Energy Forecast.
Proceedings of the Advances in Computational Intelligence, 2015

Stochastic-Based Implementation of Reservoir Computers.
Proceedings of the Advances in Computational Intelligence, 2015

Noise-robust hardware implementation of neural networks.
Proceedings of the 2015 International Joint Conference on Neural Networks, 2015

2014
Studying the Role of Synchronized and Chaotic Spiking Neural Ensembles in Neural Information Processing.
Int. J. Neural Syst., 2014

Low-cost hardware implementation of Reservoir Computers.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

Stochastic Spiking Neural Networks at the EDGE of CHAOS.
Proceedings of the 2014 International Joint Conference on Neural Networks, 2014

2012
Hardware Implementation of Stochastic Spiking Neural Networks.
Int. J. Neural Syst., 2012

Probabilistic-based neural network implementation.
Proceedings of the 2012 International Joint Conference on Neural Networks (IJCNN), 2012

Multi-subject Project Based Learning initiative.
Proceedings of the IEEE Global Engineering Education Conference, 2012

2010
Stochastic-based pattern-recognition analysis.
Pattern Recognit. Lett., 2010

Hardware implementation of stochastic-based Neural Networks.
Proceedings of the International Joint Conference on Neural Networks, 2010

2009
Chaos-Based Mixed Signal Implementation of Spiking Neurons.
Int. J. Neural Syst., 2009

Practical Hardware Implementation of Self-configuring Neural Networks.
Proceedings of the Advances in Neural Networks, 2009

Spiking Neural Network Self-configuration for Temporal Pattern Recognition Analysis.
Proceedings of the Artificial Neural Networks, 2009

2008
Self-configuring spiking neural networks.
IEICE Electron. Express, 2008

A simple CMOS chaotic integrated circuit.
IEICE Electron. Express, 2008

Using stochastic logic for efficient pattern recognition analysis.
Proceedings of the International Joint Conference on Neural Networks, 2008

2006
A Fully CMOS Low-Cost Chaotic Neural Network.
Proceedings of the International Joint Conference on Neural Networks, 2006

2005
A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs.
Proceedings of the 2005 Design, 2005

2004
A Two-Level Power-Grid Model for Transient Current Testing Evaluation.
J. Electron. Test., 2004

A BIST-based Charge Analysis for Embedded Memories.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004


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