Lukasz Lopacinski

According to our database, Lukasz Lopacinski authored at least 17 papers between 2010 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2020

A Modified Rejection-Based Architecture to Find the First Two Minima in Min-Sum-Based LDPC Decoders.

Alireza Hasani, Lukasz Lopacinski, Steffen Büchner, Jörg Nolte, Rolf Kraemer

Proceedings of the 2020 IEEE Wireless Communications and Networking Conference, 2020

2019

Data Link Layer Processor for 100 Gbps Terahertz Wireless Communications in 28 nm CMOS Technology.

Lukasz Lopacinski, Miroslav Marinkovic, Goran Panic, Mohamed Hussein Eissa, Alireza Hasani, Karthik KrishneGowda, Rolf Kraemer

IEEE Access, 2019

A Modified Shuffling Method to Split the Critical Path Delay in Layered Decoding of QC-LDPC Codes.

Alireza Hasani, Lukasz Lopacinski, Steffen Büchner, Jörg Nolte, Rolf Kraemer

Proceedings of the 30th IEEE Annual International Symposium on Personal, 2019

An Unnoticed Property in QC-LDPC Codes to Find the Message from the Codeword in Non-Systematic Codes.

Alireza Hasani, Lukasz Lopacinski, Steffen Büchner, Jörg Nolte, Rolf Kraemer

Proceedings of the European Conference on Networks and Communications, 2019

Modular Data Link Layer Processing for THz communication.

Lukasz Lopacinski, Mohamed Hussein Eissa, Goran Panic, Alireza Hasani, Rolf Kraemer

Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019

2018

Implementation of a Multi-Core Data Link Layer Processor for THz Communication.

Lukasz Lopacinski, Mohamed Hussein Eissa, Goran Panic, Marcin Brzozowski, Alireza Hasani, Rolf Kraemer

Proceedings of the 87th IEEE Vehicular Technology Conference, 2018

100 Gbit/s End-to-End Communication: Adding Flexibility with Protocol Templates.

Steffen Büchner, Alireza Hasani, Lukasz Lopacinski, Rolf Kraemer, Jörg Nolte

Proceedings of the 43rd IEEE Conference on Local Computer Networks, 2018

2017

Data Link Layer Considerations for Future 100 Gbps Terahertz Band Transceivers.

Lukasz Lopacinski, Marcin Brzozowski, Rolf Kraemer

Wirel. Commun. Mob. Comput., 2017

Verbesserung des Durchsatzes von drahtlosen Hochgeschwindigkeitskommunikationen.

Lukasz Lopacinski

Proceedings of the Ausgezeichnete Informatikdissertationen 2017, 2017

Towards 100 Gbps wireless communication: Investigation of FEC interleavers for PSSS-15 spreading.

Lukasz Lopacinski, Karthik KrishneGowda

Proceedings of the IEEE EUROCON 2017 -17th International Conference on Smart Technologies, 2017

2016

Improved turbo product coding dedicated for 100 Gbps wireless terahertz communication.

Lukasz Lopacinski, Jörg Nolte, Steffen Büchner, Marcin Brzozowski, Rolf Kraemer

Proceedings of the 27th IEEE Annual International Symposium on Personal, 2016

100 Gbit/s End-to-End Communication: Designing Scalable Protocols with Soft Real-Time Stream Processing.

Steffen Büchner, Lukasz Lopacinski, Jörg Nolte, Rolf Kraemer

Proceedings of the 41st IEEE Conference on Local Computer Networks, 2016

Towards 100 Gbps wireless communication: Energy efficiency of ARQ, FEC, and RF-frontends.

Lukasz Lopacinski, Steffen Büchner, Jörg Nolte, Marcin Brzozowski, Rolf Kraemer

Proceedings of the International Symposium on Wireless Communication Systems, 2016

2015

Challenges for 100 Gbit/s end to end communication: Increasing throughput through parallel processing.

Steffen Büchner, Jörg Nolte, Rolf Kraemer, Lukasz Lopacinski, Reinhardt Karnapke

Proceedings of the 40th IEEE Conference on Local Computer Networks, 2015

Parallel RS Error Correction Structures Dedicated for 100 Gbps Wireless Data Link Layer.

Lukasz Lopacinski, Marcin Brzozowski, Jörg Nolte, Rolf Kraemer, Steffen Büchner

Proceedings of the IEEE International Conference on Ubiquitous Wireless Broadband, 2015

Design and Implementation of an Adaptive Algorithm for Hybrid Automatic Repeat Request.

Lukasz Lopacinski, Jörg Nolte, Steffen Büchner, Marcin Brzozowski, Rolf Kraemer

Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

2010

Low power sensor node processor architecture.

Goran Panic, Thomas Basmer, Klaus Tittelbach-Helmrich, Lukasz Lopacinski

Proceedings of the 17th IEEE International Conference on Electronics, 2010