Mahmoud Zangeneh

According to our database1, Mahmoud Zangeneh authored at least 9 papers between 2009 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2016
Designing Tunable Subthreshold Logic Circuits Using Adaptive Feedback Equalization.
IEEE Trans. Very Large Scale Integr. Syst., 2016

2015
Dictionary-based sparse representation for resolution improvement in laser voltage imaging of CMOS integrated circuits.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Detecting hardware trojans using backside optical imaging of embedded watermarks.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Design and Optimization of Nonvolatile Multibit 1T1R Resistive RAM.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Sub-threshold logic circuit design using feedback equalization.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2012
Performance and energy models for memristor-based 1T1R RRAM cell.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

2010
Statistical delay modeling of read operation of SRAMs due to channel length variation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
An analytical delay reduction strategy for buffer-inserted global interconnects in VDSM technologies.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

Design of a two-capacitor sample & hold circuit using a two-stage OTA with hybrid cascode compensation.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009


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