Behjat Forouzandeh

Affiliations:
  • University of Tehran, Iran


According to our database1, Behjat Forouzandeh authored at least 32 papers between 2006 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Image Interpolation Based on 2D-DWT with Novel Regularity-Preserving Algorithm Using RLS Adaptive Filters.
Int. J. Image Graph., September, 2023

Novel low-power pipelined DCT processor for real-time IoT applications.
J. Real Time Image Process., June, 2023

2022
Image interpolation based on 2D-DWT and HDP-HMM.
Pattern Anal. Appl., 2022

Low-power hardware-efficient memory-based DCT processor.
J. Real Time Image Process., 2022

Low Complexity Multiplierless Welch Estimator Based on Memory-Based FFT.
J. Circuits Syst. Comput., 2022

2020
An O(1) time complexity sorting network for small number of inputs with hardware implementation.
Microprocess. Microsystems, 2020

2019
FPGA implementation of an adaptive window size image impulse noise suppression system.
J. Real Time Image Process., 2019

2017
A Hybrid Time Borrowing Technique to Improve the Performance of Digital Circuits in the Presence of Variations.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Improved Range Analysis in Fixed-Point Polynomial Data-Path.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

2016
UAFEA: Unified Analytical Framework for IA/AA-Based Error Analysis of Fixed-Point Polynomial Specifications.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

Analysis of stress effects on timing of nano-scaled CMOS digital integrated circuits.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

2015
A 0.8-V supply bulk-driven operational transconductance amplifier and Gm-C filter in 0.18 µm CMOS process.
Int. J. Circuit Theory Appl., 2015

A Timing Error Mitigation Technique for High Performance Designs.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

2014
A Low-Power Enhanced Bitmask-Dictionary Scheme for Test Data Compression.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

A mathematical model for estimating acceptable ratio of test patterns.
Proceedings of the 2014 East-West Design & Test Symposium, 2014

2013
Hybrid history-based test overlapping to reduce test application time.
Proceedings of the East-West Design & Test Symposium, 2013

2012
A 12.5 Gb/s 6.6 mW receiver with analog equalizer and 1-tap DFE.
Microelectron. J., 2012

High-performance low-leakage regions of nano-scaled CMOS digital gates under variations of threshold voltage and mobility.
J. Zhejiang Univ. Sci. C, 2012

Statistical estimation of leakage power dissipation in nano-scale complementary metal oxide semiconductor digital circuits using generalised extreme value distribution.
IET Circuits Devices Syst., 2012

G4-FET modeling for circuit simulation by adaptive neuro-fuzzy training systems.
IEICE Electron. Express, 2012

2011
Finding optimum value of numerical aperture for the best aerial image quality.
IEICE Electron. Express, 2011

Chip Level Statistical Leakage Power Estimation Using Generalized Extreme Value Distribution.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

Quantum Division Circuit Based on Restoring Division Algorithm.
Proceedings of the Eighth International Conference on Information Technology: New Generations, 2011

A 12.5Gb/s active-inductor based transmitter for I/O applications.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010
A novel ultra low-energy sub-threshold inverter based on nanoscale Field Effect Diode.
IEICE Electron. Express, 2010

Low-power and high-performance Automatic Gain Control systems based on nanoscale Field Effect Diode and SOI-MOSFET.
IEICE Electron. Express, 2010

Statistical delay modeling of read operation of SRAMs due to channel length variation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Low-power variable gain amplifier with wide UGBW based on nanoscale Field Effect Diode.
IEICE Electron. Express, 2009

Design of a two-capacitor sample & hold circuit using a two-stage OTA with hybrid cascode compensation.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

2008
Delay testing of PD-SOI circuits.
IEICE Electron. Express, 2008

2007
Modified analytical model for subthreshold current in short channel MOSFET's.
IEICE Electron. Express, 2007

2006
A Novel Low Power NOR gate in SOI CMOS Technology.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006


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