Makoto Noda

According to our database, Makoto Noda authored at least 9 papers between 1990 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2013

Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver With Low-Power Analog and Digital Baseband Circuitry.

Kenichi Okada, Keitarou Kondou, Masaya Miyahara, Masashi Shinagawa, Hiroki Asada, Ryo Minami, Tatsuya Yamaguchi, Ahmed Musa, Yuuki Tsukui, Yasuo Asakura, Shinya Tamonoki, Hiroyuki Yamagishi, Yasufumi Hino, Takahiro Sato, Hironori Sakaguchi, Naoki Shimasaki, Toshihiko Ito, Yasuaki Takeuchi, Ning Li, Qinghong Bu, Rui Murakami, Keigo Bunsen, Kota Matsushita, Makoto Noda, Akira Matsuzawa

IEEE J. Solid State Circuits, 2013

2012

A full 4-channel 6.3Gb/s 60GHz direct-conversion transceiver with low-power analog and digital baseband circuitry.

Kenichi Okada, Keitarou Kondou, Masaya Miyahara, Masashi Shinagawa, Hiroki Asada, Ryo Minami, Tatsuya Yamaguchi, Ahmed Musa, Yuuki Tsukui, Yasuo Asakura, Shinya Tamonoki, Hiroyuki Yamagishi, Yasufumi Hino, Takahiro Sato, Hironori Sakaguchi, Naoki Shimasaki, Toshihiko Ito, Yasuaki Takeuchi, Ning Li, Qinghong Bu, Rui Murakami, Keigo Bunsen, Kota Matsushita, Makoto Noda, Akira Matsuzawa

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011

A 60-GHz 16QAM/8PSK/QPSK/BPSK Direct-Conversion Transceiver for IEEE802.15.3c.

Kenichi Okada, Ning Li, Kota Matsushita, Keigo Bunsen, Rui Murakami, Ahmed Musa, Takahiro Sato, Hiroki Asada, Naoki Takayama, Shogo Ito, Win Chaivipas, Ryo Minami, Tatsuya Yamaguchi, Yasuaki Takeuchi, Hiroyuki Yamagishi, Makoto Noda, Akira Matsuzawa

IEEE J. Solid State Circuits, 2011

2010

A new parallel algorithm for full-digital phase-locked loop for high-throughput carrier and timing recovery systems.

Keitarou Kondou, Makoto Noda

Proceedings of the 17th IEEE International Conference on Electronics, 2010

1991

0.5- mu m 2 M-transistor BiPNMOS channelless gate array.

Hiroyuki Hara, Takayasu Sakurai, Makoto Noda, Tetsu Nagamatsu, Katsuhiro Seta, Hiroshi Momose, Yoichirou Niitsu, Hiroyuki Miyakawa, Yoshinori Watanabe

IEEE J. Solid State Circuits, November, 1991

A 0.8- mu m BiCMOS ATM switch on an 800 Mb/s asynchronous buffered banyan network.

Kenji Sakaue, Yasuro Shobatake, Masahiko Motoyama, Yoshinari Kumaki, Satoru Takatsuka, Shigeru Tanaka, Hiroyuki Hara, Kouji Matsuda, Shuji Kitaoka, Makoto Noda, Youichiro Niitsu, Masayuki Norishima, Hiroshi Momose, Kenji Maeguchi, Manabu Ishibe, Shoichi Shimizu, Toshikazu Kodama

IEEE J. Solid State Circuits, August, 1991

A 10 ns 54*54 b parallel structured full array multiplier with 0.5 mu m CMOS technology.

Junji Mori, Masato Nagamatsu, Masashi Hirano, Shigeru Tanaka, Makoto Noda, Yoshiaki Toyoshima, Kazuhiro Hashimoto, Hiroyuki Hayashida, Kenji Maeguchi

IEEE J. Solid State Circuits, April, 1991

A One-Chip Scalable 8 * 8 ATM Switch LSI Employing Shared Buffer Architecture.

Yasuro Shobatake, Masahiko Motoyama, Emiko Shobatake, Takashi Kamitake, Shoichi Shimizu, Makoto Noda, Kenji Sakaue

IEEE J. Sel. Areas Commun., 1991

1990

A single-power-supply 10-b video BiCMOS sample-and-hold IC.

Kazunori Tsugaru, Yasuhiuro Sugimoto, Makoto Noda, Takao Ito, Yoshito Suwa

IEEE J. Solid State Circuits, June, 1990