Masaya Miyahara

According to our database1, Masaya Miyahara authored at least 74 papers between 2007 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance.
IEEE J. Solid State Circuits, 2019

Type-I Digital Ring-Based PLL Using Loop Delay Compensation and ADC-Based Sampling Phase Detector.
IEICE Trans. Electron., 2019

An IoT Sensor Node SoC with Dynamic Power Scheduling for Sustainable Operation in Energy Harvesting Environment.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018
A 12.8-ns-Latency DDFS MMIC With Frequency, Phase, and Amplitude Modulations in 65-nm CMOS.
IEEE J. Solid State Circuits, 2018

A 72.4dB-SNDR 20MHz-Bandwidth Continuous-Time ΔΣ ADC with High-Linearity Gm-Cells.
IEICE Trans. Electron., 2018

A 7GS/s Complete-DDFS-Solution in 65nm CMOS.
IEICE Trans. Electron., 2018

SAR+ΔΣ ADCs with open-loop integrator using dynamic amplifier.
IEICE Electron. Express, 2018

A 64μs Start-Up 26/40MHz Crystal Oscillator with Negative Resistance Boosting Technique Using Reconfigurable Multi-Stage Amplifier.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

2017
64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay.
IEEE J. Solid State Circuits, 2017

A Wide Bandwidth Current Mode Filter Technique Using High Power Efficiency Current Amplifiers with Complementary Input.
IEICE Trans. Electron., 2017

High Resolution Mixed-Domain Delta-Sigma Time-to-Digital Converter Using Compensated Charge-Pump Integrator.
IEICE Trans. Electron., 2017

24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

A 7GS/s direct digital frequency synthesizer with a two-times interleaved RDAC in 65nm CMOS.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

An 84 dB dynamic range 62.5-625 kHz bandwidth clock-scalable noise-shaping SAR ADC with open-loop integrator using dynamic amplifier.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A high-speed DDFS MMIC with frequency, phase and amplitude modulations in 65nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017


SAR+ΔΣ ADC with open-loop integrator using dynamic amplifier.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
A 9-bit 1.8 GS/s 44 mW Pipelined ADC Using Linearized Open-Loop Amplifiers.
IEEE J. Solid State Circuits, 2016

A 3.6 GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC.
IEEE J. Solid State Circuits, 2016

A 2.2 GHz -242dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture.
IEEE J. Solid State Circuits, 2016

Highly Linear Open-Loop Amplifiers Using Nonlinearity Cancellation and Gain Adapting Techniques.
IEICE Trans. Electron., 2016

Synthesis and Automatic Layout of Resistive Digital-to-Analog Converter Based on Mixed-Signal Slice Cell.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

A Design of Op-Amp Free SAR-VCO Hybrid ADC with 2<sup>nd</sup>-Order Noise Shaping in 65nm CMOS Technology.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

A 9.35-ENOB, 14.8 fJ/conv.-step Fully-Passive Noise-Shaping SAR ADC.
IEICE Trans. Electron., 2016

Fully Passive Noise Shaping Techniques in a Charge-Redistribution SAR ADC.
IEICE Trans. Electron., 2016

A 10-bit 6.8-GS/s Direct Digital Frequency Synthesizer Employing Complementary Dual-Phase Latch-Based Architecture.
IEICE Trans. Electron., 2016

13.6 A 42Gb/s 60GHz CMOS transceiver for IEEE 802.11ay.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

A 74.9 dB SNDR 1 MHz bandwidth 0.9 mW delta-sigma time-to-digital converter using charge pump and SAR ADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A 2 GHz 3.1 mW type-I digital ring-based PLL.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

A 76-dB-DR 6.8-mW 20-MHz bandwidth CT ΔΣ ADC with a high-linearity Gm-C filter.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

A stability-improved single-opamp third-order ΣΔ modulator by using a fully-passive noise-shaping SAR ADC and passive adder.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

A 9-bit 500-MS/s 6.0-mW dynamic pipelined ADC using time-domain linearized dynamic amplifiers.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

An LO-buffer-less 60-GHz CMOS transmitter with oscillator pulling mitigation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

A 2<sup>nd</sup> order fully-passive noise-shaping SAR ADC with embedded passive gain.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
Ultralow-Voltage High-Speed Flash ADC Design Strategy Based on FoM-Delay Product.
IEEE Trans. Very Large Scale Integr. Syst., 2015

An Ultra-Low-Voltage 160 MS/s 7 Bit Interpolated Pipeline ADC Using Dynamic Amplifiers.
IEEE J. Solid State Circuits, 2015

Sub-Picosecond Resolution and High-Precision TDC for ADPLLs Using Charge Pump and SAR-ADC.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

A Circuit Technique for Enhancing Gain of Complementary Input Operational Amplifier with High Power Efficiency.
IEICE Trans. Electron., 2015

An All-Digital Reconfigurable Time-Domain ADC for Low-Voltage Sensor Interface in 65nm CMOS Technology.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

19.5 An HCI-healing 60GHz CMOS transceiver.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

25.2 A 2.2GHz -242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

A 9-bit 1.8-GS/s pipelined ADC using linearized open-loop amplifiers.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

A 3.6 GHz fractional-N digital PLL using SAR-ADC-based TDC with-110 dBc/Hz in-band phase noise.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

A novel direct digital frequency synthesizer employing complementary dual-phase latch-based architecture.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration.
IEEE J. Solid State Circuits, 2014

A 7-bit 1-GS/s Flash ADC with Background Calibration.
IEICE Trans. Electron., 2014

An Ultra-Low-Voltage, Wide Signal Swing, and Clock-Scalable Dynamic Amplifier Using a Common-Mode Detection Technique.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Injection Locked Charge-Pump PLL with a Replica of the Ring Oscillator.
IEICE Trans. Electron., 2014

20.3 A 64-QAM 60GHz CMOS transceiver with 4-channel bonding.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

22.6 A 2.2GS/s 7b 27.4mW time-based folding-flash ADC with resistively averaged voltage-to-time amplifiers.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

All-digital 0.016mm<sup>2</sup> reconfigurable sensor-ADC using 4CKES-TAD in 65nm digital CMOS.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Radio receiver front-end using time-based all-digital ADC (TAD).
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

A 0.5-to-1 V 9-bit 15-to-90 MS/s digitally interpolated pipelined-SAR ADC using dynamic amplifier.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

A dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generation.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver With Low-Power Analog and Digital Baseband Circuitry.
IEEE J. Solid State Circuits, 2013

A Time-Domain Architecture and Design Method of High Speed A-to-D Converters with Standard Cells.
IEICE Trans. Electron., 2013

A Low-Noise High-Dynamic Range Charge Sensitive Amplifier for Gas Particle Detector Pixel Readout LSIs.
IEICE Trans. Electron., 2013

Design of CMOS Low-Noise Analog Circuits for Particle Detector Pixel Readout LSIs.
IEICE Trans. Electron., 2013

A 12-bit Interpolated Pipeline ADC Using Body Voltage Controlled Amplifier.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Design of Interpolated Pipeline ADC Using Low-Gain Open-Loop Amplifiers.
IEICE Trans. Electron., 2013

A 6 bit, 7 mW, 700 MS/s Subranging ADC Using CDAC and Gate-Weighted Interpolation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

A 1 ps-resolution integrator-based time-to-digital converter using a SAR-ADC in 90nm CMOS.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

A 0.022mm<sup>2</sup> 970µW dual-loop injection-locked PLL with -243dB FOM using synthesizable all-digital PVT calibration circuits.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A 0.84ps-LSB 2.47mW time-to-digital converter using charge pump and SAR-ADC.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

A 0.55 V 7-bit 160 MS/s interpolated pipeline ADC using dynamic amplifiers.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
An Analysis on a Dynamic Amplifier and Calibration Methods for a Pseudo-Differential Dynamic Comparator.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

A 83-dB SFDR 10-MHz Bandwidth Continuous-Time Delta-Sigma Modulator Employing a One-Element-Shifting Dynamic Element Matching.
IEICE Trans. Electron., 2012

A full 4-channel 6.3Gb/s 60GHz direct-conversion transceiver with low-power analog and digital baseband circuitry.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011
A 15.5 dB, wide signal swing, dynamic amplifier using a common-mode voltage detection technique.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

An analysis on a pseudo-differential dynamic comparator with load capacitance calibration.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
An 8-Bit 600-MSps Flash ADC Using Interpolating and Background Self-Calibrating Techniques.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

2009
Development of baseband processing SoC with ultrahigh-speed QAM modem and broadband radio system for demonstration experiment thereof.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008
A Performance Model for the Design of Pipelined ADCs with Consideration of Overdrive Voltage and Slewing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

2007
The Effects of Switch Resistances on Pipelined ADC Performances and the Optimization for the Settling Time.
IEICE Trans. Electron., 2007


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