Malte Vesper

According to our database, Malte Vesper authored at least 6 papers between 2014 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2019

Dynamic streamprocessing pipelines on FPGAs targeting database acceleration.

Malte Vesper

PhD thesis, 2019

EFCAD - An Embedded FPGA CAD Tool Flow for Enabling On-chip Self-Compilation.

Khoa Dang Pham, Malte Vesper, Dirk Koch, Eddie Hung

Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

2016

JetStream: An open-source high-performance PCI Express 3 streaming library for FPGA-to-Host and FPGA-to-FPGA communication.

Malte Vesper, Dirk Koch, Kizheppatt Vipin, Suhaib A. Fahmy

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Adaptive Cache Structures.

Carsten Tradowsky, Enrique Cordero, Christoph Orsinger, Malte Vesper, Jürgen Becker

Proceedings of the Architecture of Computing Systems - ARCS 2016, 2016

A Dynamic Cache Architecture for Efficient Memory Resource Allocation in Many-Core Systems.

Carsten Tradowsky, Enrique Cordero, Christoph Orsinger, Malte Vesper, Jürgen Becker

Proceedings of the Applied Reconfigurable Computing - 12th International Symposium, 2016

2014

Towards Dynamic Cache and Bandwidth Invasion.

Carsten Tradowsky, Martin Schreiber, Malte Vesper, Ivan Domladovec, Maximilian Braun, Hans-Joachim Bungartz, Jürgen Becker

Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014