Manish Kumar Jaiswal

Integr., 2019

PACoGen: A Hardware Posit Arithmetic Core Generator.

[BibT_eX]

[DOI]

IEEE Access, 2019

2018

Fast Content Updating Algorithm for an SRAM-Based TCAM on FPGA.

[BibT_eX]

[DOI]

Farkhanda Syed

IEEE Embed. Syst. Lett., 2018

An Unified Architecture for Single, Double, Double-Extended, and Quadruple Precision Division.

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., 2018

Architecture Generator for Type-3 Unum Posit Adder/Subtractor.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Universal number posit arithmetic generator on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

2016

High-throughput cellular imaging with high-speed asymmetric-detection time-stretch optical microscopy under FPGA platform.

[BibT_eX]

[DOI]

Ho-Cheung Ng

Maolin Wang

Bob M. F. Chung

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

Dual-mode double precision division architecture.

[BibT_eX]

[DOI]

Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

Taylor Series Based Architecture for Quadruple Precision Floating Point Division.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Real-time object detection and classification for high-speed asymmetric-detection time-stretch optical microscopy on FPGA.

[BibT_eX]

[DOI]

Maolin Wang

Ho-Cheung Ng

Bob M. F. Chung

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Architecture for quadruple precision floating point division with multi-precision support.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

2015

Z-TCAM: An SRAM-based Architecture for TCAM.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Configurable Architectures for Multi-Mode Floating Point Adders.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Dual-mode double precision / two-parallel single precision floating point multiplier architecture.

[BibT_eX]

[DOI]

Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Architecture for Dual-Mode Quadruple Precision Floating Point Adder.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

2014

Unified Architecture for Double/Two-Parallel Single Precision Floating Point Adder.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2014

E-TCAM: An Efficient SRAM-Based Architecture for TCAM.

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., 2014

Series Expansion based Efficient Architectures for Double Precision Floating Point Division.

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., 2014

Configurable Architecture for Double/Two-Parallel Single Precision Floating Point Division.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

2013

Area-efficient architectures for double precision multiplier on FPGA, with run-time-reconfigurable dual single precision support.

[BibT_eX]

[DOI]

Microelectron. J., 2013

VLSI Implementation of Double-Precision Floating-Point Multiplier Using Karatsuba Technique.

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., 2013

Design space explorations of Hybrid-Partitioned TCAM (HP-TCAM).

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012

FPGA-Based High-Performance and Scalable Block LU Decomposition Architecture.

[BibT_eX]

[DOI]

Nitin Chandrachoodan

IEEE Trans. Computers, 2012

FPGA Implementation of SRAM-based Ternary Content Addressable Memory.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Area-Efficient FPGA Implementation of Quadruple Precision Floating Point Multiplier.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Area-Efficient Architectures for Large Integer and Quadruple Precision Floating Point Multipliers.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

High Performance Reconfigurable Architecture for Double Precision Floating Point Division.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

2009

Efficient Implementation of Floating-Point Reciprocator on FPGA.

[BibT_eX]

[DOI]

Nitin Chandrachoodan

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

2008

Efficient Implementation of IEEE Double Precision Floating-Point Multiplier on FPGA.

[BibT_eX]

[DOI]