Hayden KwokHay So
According to our database^{1},
Hayden KwokHay So
authored at least 69 papers
between 2005 and 2019.
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Bibliography
2019
LargeScale MultiClass ImageBased Cell Classification With Deep Learning.
IEEE J. Biomedical and Health Informatics, 2019
A RealTime Coprime Line Scan SuperResolution System for UltraFast Microscopy.
IEEE Trans. Biomed. Circuits and Systems, 2019
HighThroughput Line Buffer Microarchitecture for Arbitrary Sized Streaming Image Processing.
J. Imaging, 2019
Design of quadruple precision multiplier architectures with SIMD single and double precision support.
Integration, 2019
Computational Light Field Generation Using Deep Nonparametric Bayesian Learning.
IEEE Access, 2019
PACoGen: A Hardware Posit Arithmetic Core Generator.
IEEE Access, 2019
ELSTM: Efficient Inference of Sparse LSTM on Embedded Heterogeneous System.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
Introduction to the Special Issue on ApplicationSpecific Systems, Architectures and Processors.
Signal Processing Systems, 2018
An Unified Architecture for Single, Double, DoubleExtended, and Quadruple Precision Division.
CSSP, 2018
A DivisionFree and VariableRegularized LMSBased Generalized Sidelobe Canceller for Adaptive Beamforming and Its Efficient Hardware Realization.
IEEE Access, 2018
Architecture Generator for Type3 Unum Posit Adder/Subtractor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
PerformanceDriven System Generation for Distributed VertexCentric Graph Processing on MultiFPGA Systems.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018
Universal number posit arithmetic generator on FPGA.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
The First 25 Years of the FPL Conference: Significant Papers.
TRETS, 2017
Computationally Efficient Hyperspectral Data Learning Based on the Doubly Stochastic Dirichlet Process.
IEEE Trans. Geoscience and Remote Sensing, 2017
AreaEfficient Architecture for DualMode Double Precision Floating Point Division.
IEEE Trans. on Circuits and Systems, 2017
Computational singlecell classification using deep learning on brightfield and phase images.
Proceedings of the Fifteenth IAPR International Conference on Machine Vision Applications, 2017
Towards Flexible Automatic Generation of Graph Processing Gateware.
Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2017
Ultralow latency continuous blockparallel stream windowing using FPGA onchip memory.
Proceedings of the International Conference on Field Programmable Technology, 2017
NnCore: A parameterized nonlinear function generator for machine learning applications in FPGAs.
Proceedings of the International Conference on Field Programmable Technology, 2017
OLAF'17: Third International Workshop on Overlay Architectures for FPGAs.
Proceedings of the 2017 ACM/SIGDA International Symposium on FieldProgrammable Gate Arrays, 2017
A Parameterizable Activation Function Generator for FPGABased Neural Network Applications.
Proceedings of the 25th IEEE Annual International Symposium on FieldProgrammable Custom Computing Machines, 2017
2016
FPGA Highlevel Synthesis versus Overlay: Comparisons on Computation Kernels.
SIGARCH Computer Architecture News, 2016
Highthroughput cellular imaging with highspeed asymmetricdetection timestretch optical microscopy under FPGA platform.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016
Towards FPGAassisted spark: An SVM training acceleration case study.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016
Taylor Series Based Architecture for Quadruple Precision Floating Point Division.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Datadriven light field depth estimation using deep Convolutional Neural Networks.
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016
Sparse Hierarchical Nonparametric Bayesian learning for light field representation and denoising.
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016
Realtime object detection and classification for highspeed asymmetricdetection timestretch optical microscopy on FPGA.
Proceedings of the 2016 International Conference on FieldProgrammable Technology, 2016
GraVF: A vertexcentric distributed graph processing framework on FPGAs.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016
OLAF'16: Second International Workshop on Overlay Architectures for FPGAs.
Proceedings of the 2016 ACM/SIGDA International Symposium on FieldProgrammable Gate Arrays, 2016
VertexCentric Graph Processing on FPGA.
Proceedings of the 24th IEEE Annual International Symposium on FieldProgrammable Custom Computing Machines, 2016
Architecture for quadruple precision floating point division with multiprecision support.
Proceedings of the 27th IEEE International Conference on Applicationspecific Systems, 2016
FPGA Overlays.
Proceedings of the FPGAs for Software Programmers, 2016
2015
Configurable Architectures for MultiMode Floating Point Adders.
IEEE Trans. on Circuits and Systems, 2015
Dualmode double precision / twoparallel single precision floating point multiplier architecture.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015
Architecture for DualMode Quadruple Precision Floating Point Adder.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Accelerated cell imaging and classification on FPGAs for quantitativephase asymmetricdetection timestretch optical microscopy.
Proceedings of the 2015 International Conference on Field Programmable Technology, 2015
QuickDough: A rapid FPGA loop accelerator design framework using soft CGRA overlay.
Proceedings of the 2015 International Conference on Field Programmable Technology, 2015
Significant papers from the first 25 years of the FPL conference.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015
Automatic Soft CGRA Overlay Customization for HighProductivity Nested Loop Acceleration on FPGAs.
Proceedings of the 23rd IEEE Annual International Symposium on FieldProgrammable Custom Computing Machines, 2015
2014
Mixedarchitecture process scheduling on tightly coupled reconfigurable computers.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014
Scheduling MixedArchitecture Processes in Tightly Coupled FPGACPU Reconfigurable Computers.
Proceedings of the 22nd IEEE Annual International Symposium on FieldProgrammable Custom Computing Machines, 2014
Mapreduce processing of kmeans algorithm with FPGAaccelerated computer cluster.
Proceedings of the IEEE 25th International Conference on ApplicationSpecific Systems, 2014
2013
Design space exploration for sparse matrixmatrix multiplication on FPGAs.
I. J. Circuit Theory and Applications, 2013
Direct virtual memory access from FPGA for highproductivity heterogeneous computing.
Proceedings of the 2013 International Conference on FieldProgrammable Technology, 2013
A Soft CoarseGrained Reconfigurable Array Based Highlevel Synthesis Methodology: Promoting Design Productivity and Exploring Extreme FPGA Frequency.
Proceedings of the 21st IEEE Annual International Symposium on FieldProgrammable Custom Computing Machines, 2013
2012
Energyefficient dataflow computations on FPGAs using applicationspecific coarsegrain architecture synthesis.
SIGARCH Computer Architecture News, 2012
Design considerations of realtime adaptive beamformer for medical ultrasound research using FPGA and GPU.
Proceedings of the 2012 International Conference on FieldProgrammable Technology, 2012
Extending BORPH for shared memory reconfigurable computers.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012
Operation scheduling and architecture cosynthesis for energyefficient dataflow computations on FPGAs (abstract only).
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012
2011
Design space exploration of adaptive beamforming acceleration for bedside and portable medical ultrasound imaging.
SIGARCH Computer Architecture News, 2011
Medical Ultrasound Imaging: To GPU or Not to GPU?
IEEE Micro, 2011
On IIRbased bitstream multipliers.
I. J. Circuit Theory and Applications, 2011
A Model for Matrix Multiplication Performance on FPGAs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011
A Model for Peak Matrix Performance on FPGAs.
Proceedings of the IEEE 19th Annual International Symposium on FieldProgrammable Custom Computing Machines, 2011
2010
Zeroconfiguration identitybased IP network encryptor.
IEEE Trans. Consumer Electronics, 2010
Dynamic power reduction of FPGAbased reconfigurable computers using precomputation.
SIGARCH Computer Architecture News, 2010
Design space exploration for sparse matrixmatrix multiplication on FPGAs.
Proceedings of the International Conference on FieldProgrammable Technology, 2010
2009
Operation scheduling for FPGAbased reconfigurable computers.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009
2008
A unified hardware/software runtime environment for FPGAbased reconfigurable computers using BORPH.
ACM Trans. Embedded Comput. Syst., 2008
Quadlevel bitstream signal processing on FPGAs.
Proceedings of the 2008 International Conference on FieldProgrammable Technology, 2008
File system access from reconfigurable FPGA hardware processes in BORPH.
Proceedings of the FPL 2008, 2008
Direct sigmadelta modulated signal processing in FPGA.
Proceedings of the FPL 2008, 2008
Runtime Filesystem Support for Reconfigurable FPGA Hardware Processes in BORPH.
Proceedings of the 16th IEEE International Symposium on FieldProgrammable Custom Computing Machines, 2008
2007
ASIC Design and Verification in an FPGA Environment.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
Improving Usability of FPGABased Reconfigurable Computers Through Operating System Support.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006
A unified hardware/software runtime environment for FPGAbased reconfigurable computers using BORPH.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006
2005
An integrated debugging environment for reprogrammble hardware systems.
Proceedings of the Sixth International Workshop on Automated Debugging, 2005