Kolin Paul

Orcid: 0000-0001-6970-5509

According to our database1, Kolin Paul authored at least 133 papers between 1998 and 2024.

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Bibliography

2024
Demonstration of denial of charging attack on electric vehicle charging infrastructure and its consequences.
Int. J. Crit. Infrastructure Prot., 2024

Medical Image Data Provenance for Medical Cyber-Physical System.
CoRR, 2024

Long Short Term Memory (LSTM)-based Cuffless Continuous Blood Pressure Monitoring.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

LLC Block Reuse Predictor Design using Deep Learning to Mitigate Soft Error in Multicore.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

MMTS: Multi-Modal Time Series Based Decision Support System for Ventilator Associated Pneumonia.
Proceedings of the International Joint Conference on Neural Networks, 2024

2023
Deep Learning-assisted Retinopathy of Prematurity (ROP) Screening.
ACM Trans. Comput. Heal., July, 2023

Fundus Imaging-Based Healthcare: Present and Future.
ACM Trans. Comput. Heal., July, 2023

Deep-learning-based data-manipulation attack resilient supervisory backup protection of transmission lines.
Neural Comput. Appl., March, 2023

Energy efficiency in multicore shared cache by fault tolerance using a genetic algorithm based block reuse predictor.
Microprocess. Microsystems, 2023

Device Fingerprinting for Cyber-Physical Systems: A Survey.
ACM Comput. Surv., 2023

Compression of Large LSTM Networks for Inference on Space Constraint Systems.
Proceedings of the Pattern Recognition and Machine Intelligence, 2023

Deep Learning Assisted Plus Disease Screening of Retinal Image of Infants.
Proceedings of the 16th International Joint Conference on Biomedical Engineering Systems and Technologies, 2023

2022
Denial-of-Service Attacks Pre-Emptive and Detection Framework for Synchrophasor Based Wide Area Protection Applications.
IEEE Syst. J., 2022

SmartPatch: A patch prioritization framework.
Comput. Ind., 2022

Minimizing Off-Chip Memory Access for CNN Accelerators.
IEEE Consumer Electron. Mag., 2022

SACC: Split and Combine Approach to Reduce the Off-chip Memory Accesses of LSTM Accelerators.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Improved Blood Vessels Segmentation of Retinal Image of Infants.
Proceedings of the 15th International Joint Conference on Biomedical Engineering Systems and Technologies, 2022

Improved Blood Vessels Segmentation of Infant Retinal Image.
Proceedings of the Biomedical Engineering Systems and Technologies, 2022

2021
Architecture and security of SCADA systems: A review.
Int. J. Crit. Infrastructure Prot., 2021

Design Space Exploration of FPGA-Based System With Multiple DNN Accelerators.
IEEE Embed. Syst. Lett., 2021

Global Monitor using SpatioTemporally Correlated Local Monitors.
Proceedings of the 20th IEEE International Symposium on Network Computing and Applications, 2021

DevFing: Robust LCR Based Device Fingerprinting.
Proceedings of the 10th Mediterranean Conference on Embedded Computing, 2021

Scheduling Persistent and Fully Cooperative Instructions.
Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

Deep Learning Assisted Retinopathy of Prematurity Screening Technique.
Proceedings of the 14th International Joint Conference on Biomedical Engineering Systems and Technologies, 2021

DL-Assisted ROP Screening Technique.
Proceedings of the Biomedical Engineering Systems and Technologies, 2021

2020
Guest Editorial: Special Issue on Architectures and Design Methods for Neural Networks.
J. Signal Process. Syst., 2020

IoT-PEN: An E2E Penetration Testing Framework for IoT.
J. Inf. Process., 2020

Airmed: Efficient Self-Healing Network of Low-End Devices.
CoRR, 2020

Denial-of-Service Resilient Frameworks for Synchrophasor-Based Wide Area Monitoring Systems.
Computer, 2020

Early RTL Analysis for SCA Vulnerability in Fuzzy Extractors of Memory-Based PUF Enabled Devices.
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

Bus Width Aware Off-Chip Memory Access Minimization for CNN Accelerators.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

NV-SP: A New High Performance and Low Energy NVM-Based Scratch Pad.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Geodetic Distance and Dynamic Outlier Exclusion in EM Optimization of Self Exciting Point Process for Homicide Prediction in Chicago.
Proceedings of the 9th International Congress on Advanced Applied Informatics, 2020

IoT-PEN: A Penetration Testing Framework for IoT.
Proceedings of the 2020 International Conference on Information Networking, 2020

A Security Verification Template to Assess Cache Architecture Vulnerabilities.
Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2020

Detection and Mitigation of LFA Attack in SDN-IoT Network.
Proceedings of the Web, Artificial Intelligence and Network Applications, 2020

2019
DADS: Decentralized Attestation for Device Swarms.
ACM Trans. Priv. Secur., 2019

Equivalence Checking and Compaction of n-input Majority Terms Using Implicants of Majority.
J. Electron. Test., 2019

Majority Logic: Prime Implicants and n-Input Majority Term Equivalence.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Approximate Computing Applied to Bacterial Genome Identification using Self-Organizing Maps.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

PASCAL: Timing SCA Resistant Design and Verification Flow.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Penetration Testing Framework for IoT.
Proceedings of the 8th International Congress on Advanced Applied Informatics, 2019

Assessment of SCADA System Vulnerabilities.
Proceedings of the 24th IEEE International Conference on Emerging Technologies and Factory Automation, 2019

PatchRank: Ordering updates for SCADA systems.
Proceedings of the 24th IEEE International Conference on Emerging Technologies and Factory Automation, 2019

GRanDE: Graphical Representation and Design Space Exploration of Embedded Systems.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

A case for design space exploration of context-aware adaptive embedded systems: work-in-progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis Companion, 2019

2018
Suboptimal robust stabilization of discrete-time mismatched nonlinear system.
IEEE CAA J. Autom. Sinica, 2018

RiBoSOM: rapid bacterial genome identification using self-organizing map implemented on the synchoros SiLago platform.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

DAPP: Accelerating Training of DNN.
Proceedings of the 20th IEEE International Conference on High Performance Computing and Communications; 16th IEEE International Conference on Smart City; 4th IEEE International Conference on Data Science and Systems, 2018

2017
A Customized Many-Core Hardware Acceleration Platform for Short Read Mapping Problems Using Distributed Memory Interface with 3D-Stacked Architecture.
J. Signal Process. Syst., 2017

Stabilization of Uncertain Discrete-Time Linear System With Limited Communication.
IEEE Trans. Autom. Control., 2017

3D-Stacked Many-Core Architecture for Biological Sequence Analysis Problems.
Int. J. Parallel Program., 2017

Hardware acceleration of de novo genome assembly.
Int. J. Embed. Syst., 2017

MOCHA: Morphable Locality and Compression Aware Architecture for Convolutional Neural Networks.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium, 2017

Design and Development of Robots for ABU Robocon 2016.
Proceedings of the Advances in Robotics, 2017

2016
Polymorphic Configuration Architecture for CGRAs.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Dynamic core allocation for energy efficient video decoding in homogeneous and heterogeneous multicore architectures.
Future Gener. Comput. Syst., 2016

GAMS: Genome Assembly on Multi-GPU Using String Graph.
Proceedings of the 18th IEEE International Conference on High Performance Computing and Communications; 14th IEEE International Conference on Smart City; 2nd IEEE International Conference on Data Science and Systems, 2016

prasavGraph: Android based Labour Monitoring.
Proceedings of the 9th International Joint Conference on Biomedical Engineering Systems and Technologies (BIOSTEC 2016), 2016

mNetra: A Fundoscopy based Optometer.
Proceedings of the 9th International Joint Conference on Biomedical Engineering Systems and Technologies (BIOSTEC 2016), 2016

2015
Configurable Architectures for Multi-Mode Floating Point Adders.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Architecture and Implementation of Dynamic Parallelism, Voltage and Frequency Scaling (PVFS) on CGRAs.
ACM J. Emerg. Technol. Comput. Syst., 2015

Improving Map-Reduce for GPUs with cache.
Int. J. High Perform. Syst. Archit., 2015

3D-stacked many-core architecture for biological sequence analysis problems.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Fundus Imaging Based Affordable Eye Care.
Proceedings of the HEALTHINF 2015, 2015

Partial Reconfiguration for Dynamic Mapping of Task Graphs onto 2D Mesh Platform.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

Finite-time robust control of robot manipulator: a SDDRE based approach.
Proceedings of the 2015 Conference on Advances In Robotics, 2015

2014
Unified Architecture for Double/Two-Parallel Single Precision Floating Point Adder.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

Parallel distributed scalable runtime address generation scheme for a coarse grain reconfigurable computation and storage fabric.
Microprocess. Microsystems, 2014

ReKonf: Dynamically reconfigurable multiCore architecture.
J. Parallel Distributed Comput., 2014

Private reliability environments for efficient fault-tolerance in CGRAs.
Des. Autom. Embed. Syst., 2014

Series Expansion based Efficient Architectures for Double Precision Floating Point Division.
Circuits Syst. Signal Process., 2014

Accelerating Genome Assembly Using Hard Embedded Blocks in FPGAs.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014

RuRot: Run-time rotatable-expandable partitions for efficient mapping in CGRAs.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

Configurable Architecture for Double/Two-Parallel Single Precision Floating Point Division.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

A many-core hardware acceleration platform for short read mapping problem using distributed memory interface with 3D-stacked architecture.
Proceedings of the 2014 International Symposium on System-on-Chip, 2014

An event-triggered based robust control of robot manipulator.
Proceedings of the 13th International Conference on Control Automation Robotics & Vision, 2014

Energy Efficient Dynamic Core Allocation for Video Decoding in Embedded Multicore Architectures.
Proceedings of the 2014 IEEE International Conference on High Performance Computing and Communications, 2014

TransPar: Transformation based dynamic Parallelism for low power CGRAs.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Mapping Tasks to a Dynamically Reconfigurable Coarse Grained Array.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Customizable Compression Architecture for Efficient Configuration in CGRAs.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

High Level Design Approach to Accelerate De Novo Genome Assembly Using FPGAs.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Morphable Compression Architecture for Efficient Configuration in CGRAs.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

mDROID - An Affordable Android based mHealth System.
Proceedings of the HEALTHINF 2014, 2014

A Modular Android-Based Multi-sensor mHealth System.
Proceedings of the Biomedical Engineering Systems and Technologies, 2014

2013
Energy-aware fault-tolerant network-on-chips for addressing multiple traffic classes.
Microprocess. Microsystems, 2013

Accelerating 3D-FFT Using Hard Embedded Blocks in FPGAs.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Energy-aware-task-parallelism for efficient dynamic voltage, and frequency scaling, in CGRAs.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

Implementation and evaluation of configuration scrubbing on CGRAs: A case study.
Proceedings of the 2013 International Symposium on System on Chip, 2013

Energy-aware coarse-grained reconfigurable architectures using dynamically reconfigurable isolation cells.
Proceedings of the International Symposium on Quality Electronic Design, 2013

High performance 3D-FFT implementation.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Design and Implementation of High Performance Architectures with Partially Reconfigurable CGRAs.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

GGAKE: GPU Based Genome Assembly Using K-Mer Extension.
Proceedings of the 10th IEEE International Conference on High Performance Computing and Communications & 2013 IEEE International Conference on Embedded and Ubiquitous Computing, 2013

GAGM: Genome assembly on GPU using mate pairs.
Proceedings of the 20th Annual International Conference on High Performance Computing, 2013

FAssem: FPGA Based Acceleration of De Novo Genome Assembly.
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

Energy-Aware Fault-Tolerant CGRAs Addressing Application with Different Reliability Needs.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Distributed Runtime Computation of Constraints for Multiple Inner Loops.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Provenance framework for mHealth.
Proceedings of the Fifth International Conference on Communication Systems and Networks, 2013

2012
Self-adaptive Noc Power Management with Dual-level Agents - Architecture and Implementation.
Proceedings of the PECCS 2012, 2012

ReKonf: A Reconfigurable Adaptive ManyCore Architecture.
Proceedings of the 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, 2012

Performance Estimation of GPUs with Cache.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Improved Bioinformatics Processing Unit for Multiple Applications.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

reMORPH: A Runtime Reconfigurable Architecture.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011
Analyzing and Improving Performance and Energy Efficiency of Android.
J. Low Power Electron., 2011

p-QCA: A Tiled Programmable Fabric Architecture Using Molecular Quantum-Dot Cellular Automata.
ACM J. Emerg. Technol. Comput. Syst., 2011

A Reconfigurable Processor for Phylogenetic Inference.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

Improving Android Performance and Energy Efficiency.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

A Coarse-Grained Reconfigurable Processor for Sequencing and Phylogenetic Algorithms in Bioinformatics.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

Compression Based Efficient and Agile Configuration Mechanism for Coarse Grained Reconfigurable Architectures.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

Compact generic intermediate representation (CGIR) to enable late binding in coarse grained reconfigurable architectures.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Architecture and tools for programmable QCA.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

2010
Clocking-Based Coplanar Wire Crossing Scheme for QCA.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

A tiled programmable fabric using QCA.
Proceedings of the International Conference on Field-Programmable Technology, 2010

A high-level synthesis flow for custom instruction set extensions for application-specific processors.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Android on Mobile Devices: An Energy Perspective.
Proceedings of the 10th IEEE International Conference on Computer and Information Technology, 2010

2008
A Novel Approach to Compute Spatial Reuse in the Design of Custom Instructions.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Exhaustive Enumeration of Legal Custom Instructions for Extensible Processors.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

2007
Application Specific Datapath Extension with Distributed I/O Functional Units.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Silicon Compaction/Defragmentation for Partial Runtime Reconfiguration.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Recurring Pattern Identification and its Application to Instruction Set Extension.
Proceedings of the 2007 International Conference on Computer Design, 2007

2006
Defect-Aware Design Paradigm for Reconfigurable Architectures.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

A FLOPs Based Model for Performance Analysis and Scheduling of Applications for Single and Multiple CPUs.
Proceedings of the 2006 International Conference on Parallel Processing Workshops (ICPP Workshops 2006), 2006

2005
An FPGA Based Test Bed for Bio Inspired Computation.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

A 1.5-D Architecture for Back-Propagation Training.
Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, 2005

2002
Theory of Extended Linear Machines.
IEEE Trans. Computers, 2002

2000
Theory and Application of GF(2p) Cellular Automata as On-chip Test Pattern Generator.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

GF(2p) CA Based Vector Quantization for Fast Encoding of Still Images.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Scalable Pipelined Micro-Architecture for Wavelet Transform.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Application of GF(2p) CA in Burst Error Correcting Codes.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Theory and Applications of Cellular Automata for VLSI Design and Testing.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

1999
A VLSI Architecture for On-Line Image Decompression Using GF(28) Cellular Automata.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Cellular Automata Based Transform Coding for Image Compression.
Proceedings of the High Performance Computing, 1999

1998
Theory and Application of Multiple Attractor Cellular Automata for Fault Diagnosis.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998


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