Kolin Paul

IEEE Trans. Autom. Control., 2017

3D-Stacked Many-Core Architecture for Biological Sequence Analysis Problems.

[BibT_eX]

[DOI]

Int. J. Parallel Program., 2017

Hardware acceleration of de novo genome assembly.

[BibT_eX]

[DOI]

Syed Mohammad Asad Hassan Jafri

Dominique Lavenier

Int. J. Embed. Syst., 2017

MOCHA: Morphable Locality and Compression Aware Architecture for Convolutional Neural Networks.

[BibT_eX]

[DOI]

Syed Mohammad Asad Hassan Jafri

Naeem Abbas

Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium, 2017

Design and Development of Robots for ABU Robocon 2016.

[BibT_eX]

[DOI]

Proceedings of the Advances in Robotics, 2017

2016

Polymorphic Configuration Architecture for CGRAs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Dynamic core allocation for energy efficient video decoding in homogeneous and heterogeneous multicore architectures.

[BibT_eX]

[DOI]

Future Gener. Comput. Syst., 2016

GAMS: Genome Assembly on Multi-GPU Using String Graph.

[BibT_eX]

[DOI]

Gaurav Jain

Lalchand Rathore

Proceedings of the 18th IEEE International Conference on High Performance Computing and Communications; 14th IEEE International Conference on Smart City; 2nd IEEE International Conference on Data Science and Systems, 2016

prasavGraph: Android based Labour Monitoring.

[BibT_eX]

[DOI]

Proceedings of the 9th International Joint Conference on Biomedical Engineering Systems and Technologies (BIOSTEC 2016), 2016

mNetra: A Fundoscopy based Optometer.

[BibT_eX]

[DOI]

Vijay Kumar

Proceedings of the 9th International Joint Conference on Biomedical Engineering Systems and Technologies (BIOSTEC 2016), 2016

2015

Configurable Architectures for Multi-Mode Floating Point Adders.

[BibT_eX]

[DOI]

Manish Kumar Jaiswal

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Architecture and Implementation of Dynamic Parallelism, Voltage and Frequency Scaling (PVFS) on CGRAs.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2015

Improving Map-Reduce for GPUs with cache.

[BibT_eX]

[DOI]

Arun Parakh

Int. J. High Perform. Syst. Archit., 2015

3D-stacked many-core architecture for biological sequence analysis problems.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Fundus Imaging Based Affordable Eye Care.

[BibT_eX]

Vijay Kumar

Proceedings of the HEALTHINF 2015, 2015

Partial Reconfiguration for Dynamic Mapping of Task Graphs onto 2D Mesh Platform.

[BibT_eX]

[DOI]

Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

Finite-time robust control of robot manipulator: a SDDRE based approach.

[BibT_eX]

[DOI]

Niladri Sekhar Tripathy

Indra Narayan Kar

Proceedings of the 2015 Conference on Advances In Robotics, 2015

2014

Unified Architecture for Double/Two-Parallel Single Precision Floating Point Adder.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2014

Parallel distributed scalable runtime address generation scheme for a coarse grain reconfigurable computation and storage fabric.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2014

ReKonf: Dynamically reconfigurable multiCore architecture.

[BibT_eX]

[DOI]

Rajesh Kumar Pal

Sanjiva Prasad

J. Parallel Distributed Comput., 2014

Private reliability environments for efficient fault-tolerance in CGRAs.

[BibT_eX]

[DOI]

Stanislaw J. Piestrak

Des. Autom. Embed. Syst., 2014

Series Expansion based Efficient Architectures for Double Precision Floating Point Division.

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., 2014

Accelerating Genome Assembly Using Hard Embedded Blocks in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

RuRot: Run-time rotatable-expandable partitions for efficient mapping in CGRAs.

[BibT_eX]

[DOI]

Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

Configurable Architecture for Double/Two-Parallel Single Precision Floating Point Division.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

A many-core hardware acceleration platform for short read mapping problem using distributed memory interface with 3D-stacked architecture.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Symposium on System-on-Chip, 2014

An event-triggered based robust control of robot manipulator.

[BibT_eX]

[DOI]

Niladri Sekhar Tripathy

I. N. Kar

Proceedings of the 13th International Conference on Control Automation Robotics & Vision, 2014

Energy Efficient Dynamic Core Allocation for Video Decoding in Embedded Multicore Architectures.

[BibT_eX]

[DOI]

Rajesh Kumar Pal

Sanjiva Prasad

Proceedings of the 2014 IEEE International Conference on High Performance Computing and Communications, 2014

TransPar: Transformation based dynamic Parallelism for low power CGRAs.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Mapping Tasks to a Dynamically Reconfigurable Coarse Grained Array.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Customizable Compression Architecture for Efficient Configuration in CGRAs.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

High Level Design Approach to Accelerate De Novo Genome Assembly Using FPGAs.

[BibT_eX]

[DOI]

Syed Mohammad Asad Hassan Jafri

Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Morphable Compression Architecture for Efficient Configuration in CGRAs.

[BibT_eX]

[DOI]

Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

mDROID - An Affordable Android based mHealth System.

[BibT_eX]

[DOI]

Proceedings of the HEALTHINF 2014, 2014

A Modular Android-Based Multi-sensor mHealth System.

[BibT_eX]

[DOI]

Proceedings of the Biomedical Engineering Systems and Technologies, 2014

2013

Energy-aware fault-tolerant network-on-chips for addressing multiple traffic classes.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2013

Accelerating 3D-FFT Using Hard Embedded Blocks in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Energy-aware-task-parallelism for efficient dynamic voltage, and frequency scaling, in CGRAs.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

Implementation and evaluation of configuration scrubbing on CGRAs: A case study.

[BibT_eX]

[DOI]

Stanislaw J. Piestrak

Proceedings of the 2013 International Symposium on System on Chip, 2013

Energy-aware coarse-grained reconfigurable architectures using dynamically reconfigurable isolation cells.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Quality Electronic Design, 2013

High performance 3D-FFT implementation.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Design and Implementation of High Performance Architectures with Partially Reconfigurable CGRAs.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

GGAKE: GPU Based Genome Assembly Using K-Mer Extension.

[BibT_eX]

[DOI]

Anshuj Garg

Ashutosh Jain

Proceedings of the 10th IEEE International Conference on High Performance Computing and Communications & 2013 IEEE International Conference on Embedded and Ubiquitous Computing, 2013

GAGM: Genome assembly on GPU using mate pairs.

[BibT_eX]

[DOI]

Ashutosh Jain

Anshuj Garg

Proceedings of the 20th Annual International Conference on High Performance Computing, 2013

FAssem: FPGA Based Acceleration of De Novo Genome Assembly.

[BibT_eX]

[DOI]

Dominique Lavenier

Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

Energy-Aware Fault-Tolerant CGRAs Addressing Application with Different Reliability Needs.

[BibT_eX]

[DOI]

Stanislaw J. Piestrak

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Distributed Runtime Computation of Constraints for Multiple Inner Loops.

[BibT_eX]

[DOI]

Nasim Farahini

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Provenance framework for mHealth.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Conference on Communication Systems and Networks, 2013

2012

Self-adaptive Noc Power Management with Dual-level Agents - Architecture and Implementation.

[BibT_eX]

Proceedings of the PECCS 2012, 2012

ReKonf: A Reconfigurable Adaptive ManyCore Architecture.

[BibT_eX]

[DOI]

Rajesh Kumar Pal

Sanjiva Prasad

Proceedings of the 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, 2012

Performance Estimation of GPUs with Cache.

[BibT_eX]

[DOI]

Arun Parakh

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Improved Bioinformatics Processing Unit for Multiple Applications.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

reMORPH: A Runtime Reconfigurable Architecture.

[BibT_eX]

[DOI]

Chinmaya Dash

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011

Analyzing and Improving Performance and Energy Efficiency of Android.

[BibT_eX]

[DOI]

Tapas Kumar Kundu

J. Low Power Electron., 2011

p-QCA: A Tiled Programmable Fabric Architecture Using Molecular Quantum-Dot Cellular Automata.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2011

A Reconfigurable Processor for Phylogenetic Inference.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

Improving Android Performance and Energy Efficiency.

[BibT_eX]

[DOI]

Tapas Kumar Kundu

Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

A Coarse-Grained Reconfigurable Processor for Sequencing and Phylogenetic Algorithms in Bioinformatics.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

Compression Based Efficient and Agile Configuration Mechanism for Coarse Grained Reconfigurable Architectures.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

Compact generic intermediate representation (CGIR) to enable late binding in coarse grained reconfigurable architectures.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Architecture and tools for programmable QCA.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

2010

Clocking-Based Coplanar Wire Crossing Scheme for QCA.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

A tiled programmable fabric using QCA.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2010

A high-level synthesis flow for custom instruction set extensions for application-specific processors.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Android on Mobile Devices: An Energy Perspective.

[BibT_eX]

[DOI]

Tapas Kumar Kundu

Proceedings of the 10th IEEE International Conference on Computer and Information Technology, 2010

2008

A Novel Approach to Compute Spatial Reuse in the Design of Custom Instructions.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Exhaustive Enumeration of Legal Custom Instructions for Extensible Processors.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

2007

Application Specific Datapath Extension with Distributed I/O Functional Units.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Silicon Compaction/Defragmentation for Partial Runtime Reconfiguration.

[BibT_eX]

[DOI]

Joël Porquet

Josep Llosa

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Recurring Pattern Identification and its Application to Instruction Set Extension.

[BibT_eX]

Proceedings of the 2007 International Conference on Computer Design, 2007

2006

Defect-Aware Design Paradigm for Reconfigurable Architectures.

[BibT_eX]

[DOI]

Rahul Jain

Anindita Mukherjee

Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

A FLOPs Based Model for Performance Analysis and Scheduling of Applications for Single and Multiple CPUs.

[BibT_eX]

[DOI]

Nilesh Padhariya

Dheeraj Bhardwaj

Proceedings of the 2006 International Conference on Parallel Processing Workshops (ICPP Workshops 2006), 2006

2005

An FPGA Based Test Bed for Bio Inspired Computation.

[BibT_eX]

[DOI]

Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

A 1.5-D Architecture for Back-Propagation Training.

[BibT_eX]

Sanjay V. Rajopadhye

Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, 2005

2002

Theory of Extended Linear Machines.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2002

2000

Theory and Application of GF(2p) Cellular Automata as On-chip Test Pattern Generator.

[BibT_eX]

[DOI]

Biplab K. Sikdar

Gosta Pada Biswas

Vamsi Boppana

Cliff Yang

Sobhan Mukherjee

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

GF(2p) CA Based Vector Quantization for Fast Encoding of Still Images.

[BibT_eX]

[DOI]

Ranadeep Ghosal

Biplab K. Sikdar

Santashil Pal Chaudhuri

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Scalable Pipelined Micro-Architecture for Wavelet Transform.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Application of GF(2p) CA in Burst Error Correcting Codes.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Theory and Applications of Cellular Automata for VLSI Design and Testing.

[BibT_eX]

[DOI]

Biplab K. Sikdar

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

1999

A VLSI Architecture for On-Line Image Decompression Using GF(28) Cellular Automata.

[BibT_eX]

[DOI]

P. Dutta

Prasanta Kumar Nandi

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Cellular Automata Based Transform Coding for Image Compression.

[BibT_eX]

[DOI]

Proceedings of the High Performance Computing, 1999

1998

Theory and Application of Multiple Attractor Cellular Automata for Fault Diagnosis.

[BibT_eX]

[DOI]

Santanu Chattopadhyay