Manish Kumar Jaiswal
Orcid: 0000-0002-8722-508X
According to our database1,
Manish Kumar Jaiswal
authored at least 30 papers
between 2008 and 2019.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2019
Design of quadruple precision multiplier architectures with SIMD single and double precision support.
Integr., 2019
2018
IEEE Embed. Syst. Lett., 2018
An Unified Architecture for Single, Double, Double-Extended, and Quadruple Precision Division.
Circuits Syst. Signal Process., 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
2016
High-throughput cellular imaging with high-speed asymmetric-detection time-stretch optical microscopy under FPGA platform.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Real-time object detection and classification for high-speed asymmetric-detection time-stretch optical microscopy on FPGA.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016
Architecture for quadruple precision floating point division with multi-precision support.
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Dual-mode double precision / two-parallel single precision floating point multiplier architecture.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
Circuits Syst. Signal Process., 2014
Series Expansion based Efficient Architectures for Double Precision Floating Point Division.
Circuits Syst. Signal Process., 2014
Configurable Architecture for Double/Two-Parallel Single Precision Floating Point Division.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
2013
Area-efficient architectures for double precision multiplier on FPGA, with run-time-reconfigurable dual single precision support.
Microelectron. J., 2013
VLSI Implementation of Double-Precision Floating-Point Multiplier Using Karatsuba Technique.
Circuits Syst. Signal Process., 2013
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013
2012
IEEE Trans. Computers, 2012
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012
Area-Efficient Architectures for Large Integer and Quadruple Precision Floating Point Multipliers.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012
High Performance Reconfigurable Architecture for Double Precision Floating Point Division.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012
2009
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
2008
Proceedings of the IEEE Reglon 10 Colloquium and Third International Conference on Industrial and Information Systems, 2008