Manish Rana

According to our database, Manish Rana authored at least 6 papers between 2014 and 2018.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2018

Automatic Selection of Process Corner Simulations for Faster Design Verification.

Michael Shoniker, Oleg Oleynikov, Bruce F. Cockburn, Jie Han, Manish Rana, Witold Pedrycz

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2016

Statistical analysis and design of subthreshold operation memories.

Manish Rana

PhD thesis, 2016

Statistical analysis and comparison of 2T and 3T1D e-DRAM minimum energy operation.

Manish Rana, Ramon Canal, Esteve Amat, Antonio Rubio

Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

SRAM memory margin probability failure estimation using Gaussian Process regression.

Manish Rana, Ramon Canal, Jie Han, Bruce F. Cockburn

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

2014

REEM: Failure/non-failure region estimation method for SRAM yield analysis.

Manish Rana, Ramon Canal

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

SSFB: A highly-efficient and scalable simulation reduction technique for SRAM yield analysis.

Manish Rana, Ramon Canal

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014