Ramon Canal
Orcid: 0000-0003-4542-204X
According to our database1,
Ramon Canal
authored at least 85 papers
between 1999 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2023
Deep-Learning Based Detection for Cyber-Attacks in IoT Networks: A Distributed Attack Detection Framework.
J. Netw. Syst. Manag., April, 2023
A Survey of Machine and Deep Learning Methods for Privacy Protection in the Internet of Things.
Sensors, February, 2023
J. Syst. Archit., 2023
Vitamin-V: Virtual Environment and Tool-boxing for Trustworthy Development of RISC-V based Cloud Services.
CoRR, 2023
NEUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS.
CoRR, 2023
Proceedings of the Machine Learning, Optimization, and Data Science, 2023
Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023
EUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS.
Proceedings of the IEEE European Test Symposium, 2023
Validation, Verification, and Testing (VVT) of future RISC-V powered cloud infrastructures: the Vitamin-V Horizon Europe Project perspective.
Proceedings of the IEEE European Test Symposium, 2023
VITAMIN-V: Virtual Environment and Tool-Boxing for Trustworthy Development of RISC-V Based Cloud Services.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023
2022
Small-layered Feed-Forward and Convolutional neural networks for efficient P wave earthquake detection.
Expert Syst. Appl., November, 2022
A Real-Time Error Detection (RTD) Architecture and Its Use for Reliability and Post-Silicon Validation for F/F Based Memory Arrays.
IEEE Trans. Emerg. Top. Comput., 2022
SafeDX: Standalone Modules Providing Diverse Redundancy for Safety-Critical Applications.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2022
Proceedings of the Forum on Specification & Design Languages, 2022
Proceedings of the IEEE/ACM International Workshop on Education for High Performance Computing, 2022
2021
Fast and Accurate SER Estimation for Large Combinational Blocks in Early Stages of the Design.
IEEE Trans. Sustain. Comput., 2021
A cost-efficient QoS-aware analytical model of future software content delivery networks.
Int. J. Netw. Manag., 2021
Predictive Reliability and Fault Management in Exascale Systems: State of the Art and Perspectives.
ACM Comput. Surv., 2021
IEEE Commun. Surv. Tutorials, 2021
Proceedings of the Machine Learning, Optimization, and Data Science, 2021
SRAM Arrays with Built-in Parity Computation for Real-Time Error Detection in Cache Tag Arrays.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
Microprocess. Microsystems, 2020
Proceedings of the Machine Learning, Optimization, and Data Science, 2020
Lightweight Protection of Cryptographic Hardware Accelerators against Differential Fault Analysis.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020
Proceedings of the 50th Annual IEEE-IFIP International Conference on Dependable Systems and Networks, 2020
2D Error Correction for F/F based Arrays using In-Situ Real-Time Error Detection (RTD).
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020
2019
SyRA: Early System Reliability Analysis for Cross-Layer Soft Errors Resilience in Memory Arrays of Microprocessor Systems.
IEEE Trans. Computers, 2019
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019
Protecting RSA Hardware Accelerators against Differential Fault Analysis through Residue Checking.
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019
2018
Optimization of FinFET-Based Gain Cells for Low Power Sub-<i>V</i> <sub>T</sub> Embedded DRAMs.
J. Low Power Electron., 2018
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
2017
Suitability of FinFET introduction into eDRAM cells for operate at sub-threshold level.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017
MeRLiN: Exploiting Dynamic Instruction Behavior for Fast and Accurate Microarchitecture Level Reliability Assessment.
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017
2016
Proceedings of the 2016 IEEE International Test Conference, 2016
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
J. Low Power Electron., 2015
2014
Microelectron. J., 2014
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
iRMW: A low-cost technique to reduce NBTI-dependent parametric failures in L1 data caches.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
SSFB: A highly-efficient and scalable simulation reduction technique for SRAM yield analysis.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
DRAM-based coherent caches and how to take advantage of the coherence protocol to reduce the refresh energy.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
Thread Row Buffers: Improving Memory Performance Isolation and Throughput in Multiprogrammed Environments.
IEEE Trans. Computers, 2013
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
Proceedings of the International Symposium on Quality Electronic Design, 2013
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013
Proceedings of the Euro-Par 2013: Parallel Processing Workshops, 2013
Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes.
Proceedings of the Design, Automation and Test in Europe, 2013
2012
Distributed Cooperative Caching: An Energy Efficient Memory Scheme for Chip Multiprocessors.
IEEE Trans. Parallel Distributed Syst., 2012
Integr., 2012
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
2011
TRAMS Project: Variability and Reliability of SRAM Memories in sub-22 nm Bulk-CMOS Technologies.
Proceedings of the 2nd European Future Technologies Conference and Exhibition, 2011
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011
2010
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
Elastic cooperative caching: an autonomous dynamically adaptive memory hierarchy for chip multiprocessors.
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010
Proceedings of the Euro-Par 2010 - Parallel Processing, 16th International Euro-Par Conference, Ischia, Italy, August 31, 2010
Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability.
Proceedings of the Design, Automation and Test in Europe, 2010
2009
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009
Using Coherence Information and Decay Techniques to Optimize L2 Cache Leakage in CMPs.
Proceedings of the ICPP 2009, 2009
2008
IEEE Trans. Parallel Distributed Syst., 2008
Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability.
IEEE Micro, 2008
Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 2008
2007
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 2007
2006
Design space exploration for multicore architectures: a power/performance/thermal view.
Proceedings of the 20th Annual International Conference on Supercomputing, 2006
2005
Proceedings of the Euro-Par 2005, Parallel Processing, 11th International Euro-Par Conference, Lisbon, Portugal, August 30, 2005
2004
Proceedings of the 2nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2004), 2004
2003
2001
Int. J. Parallel Program., 2001
Proceedings of the 15th international conference on Supercomputing, 2001
2000
Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 2000
Proceedings of the 14th international conference on Supercomputing, 2000
Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, 2000
1999
Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, 1999