Jie Han

IEEE Embed. Syst. Lett., December, 2023

An Energy-Efficient Binary-Interfaced Stochastic Multiplier Using Parallel Datapaths.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., September, 2023

Special Issue on Approximate Computing: Challenges, Methodologies, Algorithms, and Architectures for Dependable and Secure Systems.

[BibT_eX]

[DOI]

IEEE Des. Test, June, 2023

Approximate Processing Element Design and Analysis for the Implementation of CNN Accelerators.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., April, 2023

Guest Editorial Unconventional Computing Techniques for Emerging Technology Applications.

[BibT_eX]

[DOI]

Paul P. Sotiriadis

Josep Lluís Rosselló Sanz

M. Hassan Najafi

IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023

A Timing-Aware Configurable Adder Based on Timing Detection for Low-Voltage Computing.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023

Highly Accurate and Energy Efficient Binary-Stochastic Multipliers for Fault-Tolerant Applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, February, 2023

Hardware Efficient Weight-Binarized Spiking Neural Networks.

[BibT_eX]

[DOI]

Chengcheng Tang

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Improving Adversarial Robustness with Self-Paced Hard-Class Pair Reweighting.

[BibT_eX]

[DOI]

Pengyue Hou

Xingyu Li

Proceedings of the Thirty-Seventh AAAI Conference on Artificial Intelligence, 2023

2022

Hybrid Partial Product-Based High-Performance Approximate Recursive Multipliers.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2022

Low-Power Approximate Logarithmic Squaring Circuit Design for DSP Applications.

[BibT_eX]

[DOI]

Francisco Javier Hernandez Santiago

IEEE Trans. Emerg. Top. Comput., 2022

An Energy-Efficient Approximate Divider Based on Logarithmic Conversion and Piecewise Constant Approximation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Characterizing Approximate Adders and Multipliers for Mitigating Aging and Temperature Degradations.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A Genetic-algorithm-based Approach to the Design of DCT Hardware Accelerators.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2022

A stochastic computing architecture for local contrast and mean image thresholding algorithm.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2022

Highly accurate division and square root circuits by exploiting signal correlation in stochastic computing.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2022

A Brief Review of Logarithmic Multiplier Designs.

[BibT_eX]

[DOI]

Zijing Niu

Proceedings of the 23rd IEEE Latin American Test Symposium, 2022

A Review of Simulation Algorithms of Classical Ising Machines for Combinatorial optimization.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Adversarial Fine-tune with Dynamically Regulated Adversary.

[BibT_eX]

[DOI]

Proceedings of the International Joint Conference on Neural Networks, 2022

Upward Packet Popup for Deadlock Freedom in Modular Chiplet-Based Systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

Efficient Traveling Salesman Problem Solvers using the Ising Model with Simulated Bifurcation.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Solving traveling salesman problems via a parallel fully connected ising machine.

[BibT_eX]

[DOI]

Qichao Tao

Mohammadreza Asadikouhanjani

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Majority Logic-Based Approximate Multipliers for Error-Tolerant Applications.

[BibT_eX]

[DOI]

Proceedings of the Approximate Computing, 2022

Approximate Computing for Efficient Neural Network Computation: A Survey.

[BibT_eX]

[DOI]

Hao Zhang

Deivalakshmi Subbian

Seok-Bum Ko

Proceedings of the Approximate Computing, 2022

2021

A Survey of Stochastic Computing Neural Networks for Machine Learning Applications.

[BibT_eX]

[DOI]

IEEE Trans. Neural Networks Learn. Syst., 2021

Exploiting Asymmetry in eDRAM Errors for Redundancy-Free Error-Tolerant Design.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2021

Accelerating Stochastic Computing Using Deterministic Halton Sequences.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

High Performance CNN Accelerators Based on Hardware and Algorithm Co-Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Non-Volatile Approximate Arithmetic Circuits Using Scalable Hybrid Spin-CMOS Majority Gates.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A Deflection-Based Deadlock Recovery Framework to Achieve High Throughput for Faulty NoCs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

An Improved Logarithmic Multiplier for Energy-Efficient Neural Computing.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2021

Fast and low-power leading-one detectors for energy-efficient logarithmic computing.

[BibT_eX]

[DOI]

Shyama Gandhi

IET Comput. Digit. Tech., 2021

Dropout Prediction Variation Estimation Using Neuron Activation Strength.

[BibT_eX]

[DOI]

CoRR, 2021

Design and Implementation of a Highly Accurate Stochastic Spiking Neural Network.

[BibT_eX]

[DOI]

Chengcheng Tang

Proceedings of the IEEE Workshop on Signal Processing Systems, 2021

Absolute Subtraction and Division Circuits Using Uncorrelated Random Bitstreams in Stochastic Computing.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021

A Review of Deterministic Approaches to Stochastic Computing.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021

Solving Traveling Salesman Problems Using Ising Models with Simulated Bifurcation.

[BibT_eX]

[DOI]

Qichao Tao

Proceedings of the 18th International SoC Design Conference, 2021

A Logarithmic Floating-Point Multiplier for the Efficient Training of Neural Networks.

[BibT_eX]

[DOI]

Zijing Niu

Leibo Liu

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

2020

Improving the Accuracy and Hardware Efficiency of Neural Networks Using Approximate Multipliers.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

Achieving Flexible Global Reconfiguration in NoCs Using Reconfigurable Rings.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2020

Profile-Based Output Error Compensation for Approximate Arithmetic Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst., 2020

Aggressive Fine-Grained Power Gating of NoC Buffers.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A Novel Heuristic Search Method for Two-Level Approximate Logic Synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Approximate Arithmetic Circuits: A Survey, Characterization, and Recent Applications.

[BibT_eX]

[DOI]

Francisco Javier Hernandez Santiago

Hai Mo

Leibo Liu

Proc. IEEE, 2020

A robust wire crossing design for thermostability and fault tolerance in quantum-dot cellular automata.

[BibT_eX]

[DOI]

Yongqiang Zhang

Guangjun Xie

Microprocess. Microsystems, 2020

Design, evaluation and application of approximate-truncated Booth multipliers.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2020

A Survey of Coarse-Grained Reconfigurable Architecture and Design: Taxonomy, Challenges, and Applications.

[BibT_eX]

[DOI]

ACM Comput. Surv., 2020

High-Throughput FPGA-Based Hardware Accelerators for Deflate Compression and Decompression Using High-Level Synthesis.

[BibT_eX]

[DOI]

Morgan Ledwon

IEEE Access, 2020

Dynamic Stochastic Computing for Digital Signal Processing Applications.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

CDRing: Reconfigurable Ring Architecture by Exploiting Cycle Decomposition of Torus Topology.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

An Energy-Efficient and Noise-Tolerant Recurrent Neural Network Using Stochastic Computing.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

Low-Power Approximate Unsigned Multipliers With Configurable Error Recovery.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A High-Performance and Energy-Efficient FIR Adaptive Filter Using Approximate Distributed Arithmetic Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Lifetime Reliability-Constrained Runtime Mapping for Throughput Optimization in Many-Core Systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Low-Power Unsigned Divider and Square Root Circuit Designs Using Adaptive Approximation.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2019

Serial concatenated convolutional code encoder in quantum-dot cellular automata.

[BibT_eX]

[DOI]

Yongqiang Zhang

Guangjun Xie

Nano Commun. Networks, 2019

A Stochastic-Computing based Deep Learning Framework using Adiabatic Quantum-Flux-Parametron SuperconductingTechnology.

[BibT_eX]

[DOI]

CoRR, 2019

Design and Analysis of Majority Logic Based Approximate Radix-4 Booth Encoders.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019

Pj-AxMTJ: Process-in-memory with Joint Magnetization Switching for Approximate Computing in Magnetic Tunnel Junction.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

A stochastic-computing based deep learning framework using adiabatic quantum-flux-parametron superconducting technology.

[BibT_eX]

[DOI]

Proceedings of the 46th International Symposium on Computer Architecture, 2019

Characterizing Approximate Adders and Multipliers Optimized under Different Design Constraints.

[BibT_eX]

[DOI]

Francisco J. H. Santiago

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

A Hardware-Efficient Logarithmic Multiplier with Improved Accuracy.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Design and Evaluation of an FPGA-based Hardware Accelerator for Deflate Data Decompression.

[BibT_eX]

[DOI]

Morgan Ledwon

Proceedings of the 2019 IEEE Canadian Conference of Electrical and Computer Engineering, 2019

Approximate Leading One Detector Design for a Hardware-Efficient Mitchell Multiplier.

[BibT_eX]

[DOI]

Shyama Gandhi

Proceedings of the 2019 IEEE Canadian Conference of Electrical and Computer Engineering, 2019

Approximate Arithmetic Circuits: Design and Evaluation.

[BibT_eX]

[DOI]

Proceedings of the Approximate Circuits, Methodologies and CAD., 2019

2018

Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

Toward Energy-Efficient Stochastic Circuits Using Parallel Sobol Sequences.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

Feedback-Based Low-Power Soft-Error-Tolerant Design for Dual-Modular Redundancy.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

Design, Evaluation and Application of Approximate High-Radix Dividers.

[BibT_eX]

[DOI]

IEEE Trans. Multi Scale Comput. Syst., 2018

Automatic Selection of Process Corner Simulations for Faster Design Verification.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Gradient Descent Using Stochastic Circuits for Efficient Training of Learning Machines.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

A Stochastic Computational Multi-Layer Perceptron with Backward Propagation.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2018

A stochastic approach for the reliability evaluation of multi-state systems with dependent components.

[BibT_eX]

[DOI]

Reliab. Eng. Syst. Saf., 2018

An Energy-Efficient Online-Learning Stochastic Computational Deep Belief Network.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Low-Power Approximate Multipliers Using Encoded Partial Products and Approximate Compressors.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Stochastic Analysis of Multiplex Boolean Networks for Understanding Epidemic Propagation.

[BibT_eX]

[DOI]

IEEE Access, 2018

Approximate Arithmetic Circuits and Their Applications.

[BibT_eX]

[DOI]

Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018

A Probabilistic Error Model and Framework for Approximate Booth Multipliers.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

An area and energy efficient design of domain-wall memory-based deep convolutional neural networks using stochastic computing.

[BibT_eX]

[DOI]

Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Design and Application of an Approximate 2-D Convolver with Error Compensation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Approximate On-chip Memory Optimization Method For Deep Residual Networks.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

Leveraging Spintronic Devices for Efficient Approximate Logic and Stochastic Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

An energy-efficient stochastic computational deep belief network.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Adaptive approximation in arithmetic circuits: A low-power unsigned divider design.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

A Multi-Objective Model Oriented Mapping Approach for NoC-based Computing Systems.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2017

Algorithm and Design of a Fully Parallel Approximate Coordinate Rotation Digital Computer (CORDIC).

[BibT_eX]

[DOI]

IEEE Trans. Multi Scale Comput. Syst., 2017

Design of Approximate Radix-4 Booth Multipliers for Error-Tolerant Computing.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2017

Two Approximate Voting Schemes for Reliable Computing.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2017

A Review, Classification, and Comparative Evaluation of Approximate Arithmetic Circuits.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2017

Approximate reliability of multi-state two-terminal networks by stochastic analysis.

[BibT_eX]

[DOI]

IET Networks, 2017

A Stochastic Computational Approach for the Analysis of Fuzzy Systems.

[BibT_eX]

[DOI]

IEEE Access, 2017

Design and operational assessment of an intra-cell hybrid L2 cache.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017

Partially universal modules for high performance logic circuit design.

[BibT_eX]

[DOI]

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Evaluating Data Resilience in CNNs from an Approximate Memory Perspective.

[BibT_eX]

[DOI]

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Design of Approximate High-Radix Dividers by Inexact Binary Signed-Digit Addition.

[BibT_eX]

[DOI]

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

A true random number generator based on parallel STT-MTJs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Energy efficient stochastic computing with Sobol sequences.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Hardware ODE Solvers using Stochastic Circuits.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

An efficient hardware design for cerebellar models using approximate circuits: special session paper.

[BibT_eX]

[DOI]

Leibo Liu

Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017

2016

Stochastic Circuit Design and Performance Evaluation of Vector Quantization for Different Error Measures.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Logic-in-Memory With a Nonvolatile Programmable Metallization Cell.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Reliability Evaluation of Phased-Mission Systems Using Stochastic Computation.

[BibT_eX]

[DOI]

IEEE Trans. Reliab., 2016

Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

On the Design of Approximate Restoring Dividers for Error-Tolerant Applications.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

Reliability and Criticality Analysis of Communication Networks by Stochastic Computation.

[BibT_eX]

[DOI]

IEEE Netw., 2016

Design, evaluation and fault-tolerance analysis of stochastic FIR filters.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2016

Design of a hybrid non-volatile SRAM cell for concurrent SEU detection and correction.

[BibT_eX]

[DOI]

Integr., 2016

Introduction to approximate computing.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

A comparative evaluation of approximate multipliers.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

A fully parallel approximate CORDIC design.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Adaptive Filter Design Using Stochastic Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

A Multi-accuracy-Level Approximate Memory Architecture Based on Data Significance Analysis.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Design and evaluation of an approximate Wallace-Booth multiplier.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

SRAM memory margin probability failure estimation using Gaussian Process regression.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

A Design of a Non-Volatile PMC-Based (Programmable Metallization Cell) Register File.

[BibT_eX]

[DOI]

Salin Junsangsri

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Design and analysis of an approximate 2D convolver.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

A novel gate grading approach for soft error tolerance in combinational circuits.

[BibT_eX]

[DOI]

Ali Mahani

Proceedings of the 2016 IEEE Canadian Conference on Electrical and Computer Engineering, 2016

2015

A Flexible Energy- and Reliability-Aware Application Mapping for NoC-Based Reconfigurable Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

A Fault-Tolerant Technique Using Quadded Logic and Quadded Transistors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

On the Restore Operation in MTJ-Based Nonvolatile SRAM Cells.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

On the Nonvolatile Performance of Flip-Flop/SRAM Cells With a Single MTJ.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Efficient Fault-Tolerant Topology Reconfiguration Using a Maximum Flow Algorithm.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2015

A Stochastic Approach for the Analysis of Dynamic Fault Trees With Spare Gates Under Probabilistic Common Cause Failures.

[BibT_eX]

[DOI]

IEEE Trans. Reliab., 2015

Circuits for a Perpendicular Magnetic Anisotropic (PMA) Racetrack Memory.

[BibT_eX]

[DOI]

IEEE Trans. Multi Scale Comput. Syst., 2015

An Efficient Application Mapping Approach for the Co-Optimization of Reliability, Energy, and Performance in Reconfigurable NoC Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Design and Analysis of Approximate Compressors for Multiplication.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2015

An Analytical Framework for Evaluating the Error Characteristics of Approximate Adders.

[BibT_eX]

[DOI]

Cong Liu

IEEE Trans. Computers, 2015

Reliability-aware mapping for various NoC topologies and routing algorithms under performance constraints.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2015

A Design Approach for Compressor Based Approximate Multipliers.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on VLSI Design, 2015

Design and evaluation of stochastic FIR filters.

[BibT_eX]

[DOI]

Proceedings of the IEEE Pacific Rim Conference on Communications, 2015

Transmission gate-based approximate adders for inexact computing.

[BibT_eX]

[DOI]

Zhixi Yang

Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

Matrix multiplication by an inexact systolic array.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

A Ternary Content Addressable Cell Using a Single Phase Change Memory (PCM).

[BibT_eX]

[DOI]

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

A Comparative Review and Evaluation of Approximate Adders.

[BibT_eX]

[DOI]

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Design of Approximate Unsigned Integer Non-restoring Divider for Inexact Computing.

[BibT_eX]

[DOI]

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Approximate compressors for error-resilient multiplier design.

[BibT_eX]

[DOI]

Zhixi Yang

Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

Evaluating the impact of spike and flicker noise in phase change memories.

[BibT_eX]

[DOI]

Salin Junsangsri

Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

Minimizing the number of process corner simulations during design verification.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

An approximate voting scheme for reliable computing.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

A novel approach using a minimum cost maximum flow algorithm for fault-tolerant topology reconfiguration in NoC architectures.

[BibT_eX]

[DOI]

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

DPALS: A dynamic programming-based algorithm for two-level approximate logic synthesis.

[BibT_eX]

[DOI]

Chen Zou

Weikang Qian

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Stochastic circuit design and performance evaluation of vector quantization.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015

2014

A Stochastic Approach for the Analysis of Fault Trees With Priority AND Gates.

[BibT_eX]

[DOI]

IEEE Trans. Reliab., 2014

A Stochastic Computational Approach for Accurate and Efficient Reliability Evaluation.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2014

Stochastic Multiple-Valued Gene Networks.

[BibT_eX]

[DOI]

Peican Zhu

IEEE Trans. Biomed. Circuits Syst., 2014

Robust HSPICE modeling of a single electron turnstile.

[BibT_eX]

[DOI]

Wei Wei

Microelectron. J., 2014

Asynchronous Stochastic Boolean Networks as Gene Network Models.

[BibT_eX]

[DOI]

Peican Zhu

J. Comput. Biol., 2014

Gene perturbation and intervention in context-sensitive stochastic Boolean networks.

[BibT_eX]

[DOI]

Peican Zhu

BMC Syst. Biol., 2014

HSPICE macromodel of a Programmable Metallization Cell (PMC) and its application to memory design.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

A memristor-based TCAM (Ternary Content Addressable Memory) cell.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

An enhanced HSPICE macromodel of a PCM cell with threshold switching and recovery behavior.

[BibT_eX]

[DOI]

Linbin Chen

Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

FDSOI SRAM cells for low power design at 22nm technology node.

[BibT_eX]

[DOI]

Linbin Chen

Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

A system-level scheme for resistance drift tolerance of a multilevel phase change memory.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

A low-power, high-performance approximate multiplier with configurable partial error recovery.

[BibT_eX]

[DOI]

Cong Liu

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A hybrid non-volatile SRAM cell with concurrent SEU detection and correction.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

A 6.0-13.5 GHz Alias-Locked Loop Frequency Synthesizer in 130 nm CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

New Metrics for the Reliability of Approximate and Probabilistic Adders.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2013

Analysis of Error Masking and Restoring Properties of Sequential Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2013

A fault tolerant NoC architecture using quad-spare mesh topology and dynamic reconfiguration.

[BibT_eX]

[DOI]

J. Syst. Archit., 2013

A PCM-based TCAM cell using NDR.

[BibT_eX]

[DOI]

Hao Wu

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

A VLSI architecture for enhancing the fault tolerance of NoC using quad-spare mesh topology and dynamic reconfiguration.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Approximate computing: An emerging paradigm for energy-efficient design.

[BibT_eX]

[DOI]

Michael Orshansky

Proceedings of the 18th IEEE European Test Symposium, 2013

2012

Stochastic Boolean networks: An efficient approach to modeling gene regulatory networks.

[BibT_eX]

[DOI]

BMC Syst. Biol., 2012

Cell design and comparative evaluation of a novel 1T memristor-based memory.

[BibT_eX]

[DOI]

Vikas Sakode

Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

Design and reliability analysis of multiple valued logic gates using carbon nanotube FETs.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

Macromodeling a phase change memory (PCM) cell by HSPICE.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

Modeling a single electron turnstile in HSPICE.

[BibT_eX]

[DOI]

Wei Wei

Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Hardening a memory cell for low power operation by gate leakage reduction.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

2011

Reliability evaluation of logic circuits using probabilistic gate models.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2011

A hybrid memory cell using Single-Electron transfer.

[BibT_eX]

[DOI]

Wei Wei

Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

On the Effects of Intra-gate Resistive Open Defects in Gates at Nanoscaled CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

On the Reliable Performance of Sequential Adders for Soft Computing.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

A Transistor-Level Stochastic Approach for Evaluating the Reliability of Digital Nanometric CMOS Circuits.

[BibT_eX]

[DOI]

Hao Chen

Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

2010

Stochastic computational models for accurate reliability evaluation of logic circuits.

[BibT_eX]

[DOI]

Hao Chen

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2005

Toward Hardware-Redundant, Fault-Tolerant Logic for Nanoelectronics.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2005

Faults, Error Bounds and Reliability of Nanoelectronic Circuits.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004

From Massively Parallel Image Processors to Fault-Tolerant Nanocomputers.

[BibT_eX]

[DOI]

Pieter Jonker

Proceedings of the 17th International Conference on Pattern Recognition, 2004

2003

A Study on Fault-Tolerant Circuits Using Redundancy.

[BibT_eX]

Pieter Jonker

Proceedings of the International Conference on VLSI, 2003

2000

On Quantum and Classical Computing with Arrays of Superconducting Persistent Current Qubits.

[BibT_eX]

[DOI]

Pieter Jonker